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21. 发明授权

US08125792B2 Substrate for wiring, semiconductor device for stacking using the same, and stacked semiconductor module 有权
标题翻译：布线用基板，使用该基板的层叠用半导体装置以及叠层型半导体模块
公开(公告)号：US08125792B2
公开(公告)日：2012-02-28
申请号：US12330686
申请日：2008-12-09
申请人： Takeshi Kawabata
发明人： Takeshi Kawabata
IPC分类号： H05K7/00
CPC分类号： H05K1/0268 , H01L22/14 , H01L22/20 , H01L2224/73204 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H05K1/0298 , H05K1/112 , H05K3/0052 , H05K2203/175
摘要： In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved.
摘要翻译：在层叠半导体模块中，容易进行覆盖连接端子的测试，并且实现了高可靠性。

22. 发明申请

US20110110519A1 DATA TRANSMISSION DEVICE, DATA RECEPTION DEVICE, METHODS THEREOF, RECORDING MEDIUM, AND DATA COMMUNICATION SYSTEM THEREFOR 审中-公开
标题翻译：数据传输设备，数据接收设备，其方法，记录介质及其数据通信系统
公开(公告)号：US20110110519A1
公开(公告)日：2011-05-12
申请号：US12811862
申请日：2009-01-09
申请人： Tomoyasu Suzaki , Yukiyasu Tsunoo , Hiroyasu Kubo , Maki Shigeri , Teruo Saito , Takeshi Kawabata , Hiroki Nakashima
发明人： Tomoyasu Suzaki , Yukiyasu Tsunoo , Hiroyasu Kubo , Maki Shigeri , Teruo Saito , Takeshi Kawabata , Hiroki Nakashima
IPC分类号： H04L9/28
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24
摘要： A data transmission device (100) performs encryption processing on transmission data, performs encryption processing of a Feistel structure on the obtained first converted data, and performs processing in the relationship of an inverse function with the first encryption processing on the obtained second converted data. A first converting unit (105) divides transmission data into N sets (N being three or greater) of divided transmission data, performs operation processing on the divided transmission data to generate at least N sets of operation processing data, and combines the generated N sets of operation processing data to generate the first converted data. The first converting unit (105) selects a pair of first and second divided transmission data from the N sets of divided transmission data, performs a logical operation on the first divided transmission data and extended key data to generate a first operation result, performs an exclusive OR operation on the second divided transmission data and the first operation result to generate one set of operation processing data, performs a logical operation on the generated operation processing data and extended key data to generate a second operation result, and performs an exclusive OR operation on third divided transmission data selected from the N sets of divided transmission data and the second operation result to generate one set of the operation processing data.
摘要翻译：数据发送装置（100）对发送数据进行加密处理，对所获得的第一转换数据执行Feistel结构的加密处理，并且对获得的第二转换数据进行与第一加密处理相反的功能的处理。第一转换单元（105）将发送数据分割成分割后的发送数据的N组（N为3以上），对分割后的发送数据进行运算处理，生成至少N组运算处理数据，并将生成的N组的操作处理数据以生成第一转换数据。第一转换单元（105）从N组分割发送数据中选择一对第一和第二分割发送数据，对第一分割发送数据和扩展密钥数据执行逻辑运算，生成第一运算结果，执行排他性对第二分割发送数据和第一操作结果进行“或”运算，生成一组运算处理数据，对生成的运算处理数据和扩展密钥数据进行逻辑运算，生成第二运算结果，并对从N组分割发送数据中选择的第三分割发送数据和第二操作结果，以生成一组操作处理数据。

23. 发明授权

US07882644B2 Alignment adjusting mechanism and measuring instrument 有权
标题翻译：对准调整机构和测量仪器
公开(公告)号：US07882644B2
公开(公告)日：2011-02-08
申请号：US12787903
申请日：2010-05-26
申请人： Takeshi Kawabata , Takeshi Yamamoto
发明人： Takeshi Kawabata , Takeshi Yamamoto
IPC分类号： G01B3/00 , G01B7/03
CPC分类号： G01B5/012 , G01B7/012 , G01B21/047
摘要： An alignment mechanism includes: an adjusting plate having first and second adjustment ends parallel to an X axis direction; a probe fixing portion provided to the adjusting plate; a probe fixed to the probe fixing portion; a reinforcing plate having first and second base ends parallel to the X axis direction, displacement of the reinforcing portion in a Y axis direction being restricted; Y-direction adjusting screws for pressing the adjusting plate in the Y axis direction; and adjustment connectors for respectively connecting the first adjustment end with the first base end and the second adjustment end with the second base end. A stylus of the probe is disposed on a line of intersection of a first inclined surface including the first adjustment end and the first base end and a second inclined surface including the second adjustment end and the second base end.
摘要翻译：对准机构包括：调节板，其具有平行于X轴方向的第一调节端和第二调节端; 设置在调节板上的探针固定部; 固定到探针固定部的探针; 加强板，其具有与X轴方向平行的第一和第二基端，所述加强部在Y轴方向上的位移受到限制; Y方向调节螺丝，用于在Y轴方向上按压调节板; 以及用于分别将第一调整端与第一基端和第二调节端与第二基端连接的调节连接器。探针的触针设置在包括第一调整端和第一基端的第一倾斜表面的交叉线和包括第二调节端和第二基端的第二倾斜表面。

24. 发明授权

US07586183B2 Multilevel semiconductor module and method for fabricating the same 失效
标题翻译：多层半导体模块及其制造方法
公开(公告)号：US07586183B2
公开(公告)日：2009-09-08
申请号：US11405478
申请日：2006-04-18
申请人： Takeshi Kawabata , Motoaki Satou , Toshiyuki Fukuda , Toshio Tsuda , Kazuhiro Nobori , Seiichi Nakatani
发明人： Takeshi Kawabata , Motoaki Satou , Toshiyuki Fukuda , Toshio Tsuda , Kazuhiro Nobori , Seiichi Nakatani
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/5385 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/1627 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip and including second buried conductors electrically connected to the first buried conductors. A first resin board located at the bottom is thicker than second resin boards. Each of the sheet members includes an adhesive member covering the upper and side faces of the semiconductor chip.
摘要翻译：通过交替堆叠树脂板和片材构件形成半导体模块。每个树脂板包括第一掩埋导体。半导体芯片安装在每个树脂板的上表面上。每个片构件具有用于容纳半导体芯片的开口，并且包括电连接到第一掩埋导体的第二掩埋导体。位于底部的第一树脂板比第二树脂板厚。每个片状构件包括覆盖半导体芯片的上表面和侧面的粘合构件。

25. 发明申请

US20090147490A1 SUBSTRATE FOR WIRING, SEMICONDUCTOR DEVICE FOR STACKING USING THE SAME, AND STACKED SEMICONDUCTOR MODULE 有权
标题翻译：用于布线的基板，用于堆叠的半导体器件和堆叠半导体模块
公开(公告)号：US20090147490A1
公开(公告)日：2009-06-11
申请号：US12330686
申请日：2008-12-09
申请人： Takeshi Kawabata
发明人： Takeshi Kawabata
IPC分类号： H01R12/04 , H01L23/12
CPC分类号： H05K1/0268 , H01L22/14 , H01L22/20 , H01L2224/73204 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H05K1/0298 , H05K1/112 , H05K3/0052 , H05K2203/175
摘要： In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved.
摘要翻译：在叠层半导体模块中，容易进行覆盖连接端子的测试，并且实现了高可靠性。

26. 发明授权

US07443028B2 Imaging module and method for forming the same 有权
标题翻译：成像模块及其形成方法
公开(公告)号：US07443028B2
公开(公告)日：2008-10-28
申请号：US11369818
申请日：2006-03-08
申请人： Motoaki Satou , Takeshi Kawabata , Masatoshi Shinagawa , Toshiyuki Fukuda
发明人： Motoaki Satou , Takeshi Kawabata , Masatoshi Shinagawa , Toshiyuki Fukuda
IPC分类号： H01L23/48
CPC分类号： H01L27/14634 , H01L27/14618 , H01L27/14625 , H01L27/1469 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H04N5/2257 , H05K1/182 , H01L2224/0401
摘要： An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a second opening; a second electrically-conductive member electrically connecting the second resin board and the printed circuit board to each other; an imaging semiconductor chip mounted on the lower surface of the second resin board to cover the first opening and provided with an imaging sensor, an optical member placed on the upper surface of the second resin board to cover the first opening; a first semiconductor control chip provided with a control device for controlling operation of the imaging sensor and mounted on the lower surface of the first resin board.
摘要翻译：成像模块通过堆叠形成：第一树脂板; 具有第一开口的第二树脂板; 将第一树脂板和第二树脂板彼此电连接的第一导电构件; 具有第二开口的印刷电路板; 将第二树脂板和印刷电路板电连接的第二导电构件; 成像半导体芯片，其安装在所述第二树脂板的下表面上以覆盖所述第一开口并设置有成像传感器;光学构件，设置在所述第二树脂板的上表面上以覆盖所述第一开口; 第一半导体控制芯片，设置有用于控制成像传感器的操作并安装在第一树脂板的下表面上的控制装置。

27. 发明授权

US07195587B2 Apparatus and method using it for detecting and displaying form of insertion part of endoscope inserted into body cavity 有权
标题翻译：用于检测和显示插入体腔内窥镜插入部分的装置和方法
公开(公告)号：US07195587B2
公开(公告)日：2007-03-27
申请号：US10684544
申请日：2003-10-14
申请人： Akira Taniguchi , Sumihiro Uchimura , Yasuhiro Yoshizawa , Takeshi Kawabata , Masanao Hara , Kazutaka Tsuji , Chieko Aizawa
发明人： Akira Taniguchi , Sumihiro Uchimura , Yasuhiro Yoshizawa , Takeshi Kawabata , Masanao Hara , Kazutaka Tsuji , Chieko Aizawa
IPC分类号： A61B1/04
CPC分类号： A61B5/064 , A61B5/06 , A61B5/065
摘要： A shape of endoscope detecting apparatus in accordance with the present invention consists mainly of a shape detection unit, a marker, a location information of marker acquisition unit, and a display control unit. The shape detection unit detects the shape of a portion of an insertion unit of an endoscope inserted into a subject, and produces graphic data expressing the shape thereof. The marker is placed near a position on the subject at which the endoscope is inserted. The location information of marker acquisition unit acquires the location information of the marker. The display control unit graphically indicates on a display device the shape of the portion inserted into a body cavity, which is detected by the shape detection unit, using as a reference the location information of the marker acquired by the location information of marker acquisition unit.
摘要翻译：根据本发明的内窥镜检测装置的形状主要包括形状检测单元，标记，标记获取单元的位置信息和显示控制单元。形状检测单元检测插入到被检体内的内窥镜的插入单元的一部分的形状，并且生成表示其形状的图形数据。将标记放置在被插入物体的位置附近。标记获取单元的位置信息获取标记的位置信息。显示控制单元以图形方式在显示装置上使用由形状检测单元检测的插入到体腔中的部分的形状，以标记获取单元的位置信息获取的标记的位置信息作为参考。

28. 发明授权

US07154189B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US07154189B2
公开(公告)日：2006-12-26
申请号：US11035986
申请日：2005-01-18
申请人： Kenji Maeda , Takashi Takata , Takao Ochi , Hiroki Naraoka , Takeshi Kawabata , Yoshiyuki Arai , Shigeru Nonoyama , Hajime Homma
发明人： Kenji Maeda , Takashi Takata , Takao Ochi , Hiroki Naraoka , Takeshi Kawabata , Yoshiyuki Arai , Shigeru Nonoyama , Hajime Homma
IPC分类号： H01L23/29 , H01L23/31
CPC分类号： H05K1/186 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13155 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/92125 , H01L2224/97 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/15787 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/3511 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.

29. 发明申请

US20060231939A1 Multilevel semiconductor module and method for fabricating the same 失效
公开(公告)号：US20060231939A1
公开(公告)日：2006-10-19
申请号：US11405478
申请日：2006-04-18
申请人： Takeshi Kawabata , Motoaki Satou , Toshiyuki Fukuda , Toshio Tsuda , Kazuhiro Nobori , Seiichi Nakatani
发明人： Takeshi Kawabata , Motoaki Satou , Toshiyuki Fukuda , Toshio Tsuda , Kazuhiro Nobori , Seiichi Nakatani
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/5385 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/1627 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip and including second buried conductors electrically connected to the first buried conductors. A first resin board located at the bottom is thicker than second resin boards. Each of the sheet members includes an adhesive member covering the upper and side faces of the semiconductor chip.

30. 发明申请

US20060010308A1 Microprocessor 有权
标题翻译：微处理器
公开(公告)号：US20060010308A1
公开(公告)日：2006-01-12
申请号：US11175296
申请日：2005-07-07
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30123 , G06F9/485
摘要： A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
摘要翻译：微处理器执行流水线架构中的程序，其包括任务寄存器管理单元，该任务寄存器管理单元将任务寄存器的值切换到在完成第一任务的执行之后执行第二任务时所使用的第二寄存器信息，如果切换指令当多个单元执行第一任务时发出第二任务;以及任务管理器，其在将值切换到第二登记信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个多个单元允许执行第二任务。

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