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    • 22. 发明授权
    • Method and apparatus for designing integrated circuits according to
master slice approach
    • 根据主切片方法设计集成电路的方法和装置
    • US5551014A
    • 1996-08-27
    • US396789
    • 1995-03-01
    • Kazuhiro YoshidaNoriaki Sato
    • Kazuhiro YoshidaNoriaki Sato
    • H01L21/82G06F17/50H01L27/02H01L27/118G06F15/00G06F13/00
    • H01L27/0207G06F17/5068
    • A CAD system designs mask patterns for use in a master slice integrated circuit processing. The system includes an input device such as a mouse interface, and a display unit for symbolically displaying circuit elements and cells. A first data base stores a net list of circuit design information. A second data base stores data relating to the structure of a master slice bulk and various types of elemental cells formed in the master slice. A processing unit of the CAD system causes the display unit to display both a circuit design scheme and the master slice bulk on a screen of the display unit. The processing unit produces data about the initial positions of a pair of contact hole patterns by which a resistor is defined in a resistive cell region of the master slice, and automatically shifts the contact hole patterns from the initial positions to another position, in order to avoid interference between a wiring pattern on the master slice bulk and the contact hole patterns.
    • CAD系统设计用于主切片集成电路处理的掩模图案。 该系统包括诸如鼠标接口的输入设备和用于象征性地显示电路元件和单元的显示单元。 第一数据库存储电路设计信息的网络列表。 第二数据库存储与主切片体的结构相关的数据和形成在主切片中的各种类型的元素。 CAD系统的处理单元使得显示单元在显示单元的屏幕上同时显示电路设计方案和主切片块。 处理单元产生关于一对接触孔图案的初始位置的数据,通过该初始位置在主切片的电阻单元区域中限定电阻器,并且将接触孔图案自动地从初始位置移位到另一位置,以便 避免主片体上的布线图案与接触孔图案之间的干涉。
    • 24. 发明授权
    • Method of fabricating a metal-oxide-semiconductor device having a
semiconductor on insulator (SOI) structure
    • 制造具有绝缘体上半导体(SOI)结构的金属氧化物半导体器件的方法
    • US5238857A
    • 1993-08-24
    • US893067
    • 1992-06-03
    • Noriaki SatoKazunori Imaoka
    • Noriaki SatoKazunori Imaoka
    • H01L21/336H01L29/786
    • H01L29/66772H01L29/78609H01L29/78654
    • A metal-oxide-semiconductor device having a semiconductor-on-insulator structure comprises an insulator substrate; a single crystal semiconductor substrate provided on the insulator substrate, the single crystal semiconductor substrate and the insulator substrate forming a part of the semiconductor-on-insulator structure; source and drain regions doped to a first conduction type and defined in the single crystal semiconductor substrate; a channel region defined in the single crystal semiconductor substrate so as to be interposed between the source and drain regions, the channel region being doped to a second conduction type opposite to the first conduction type with a first impurity concentration level; a gate insulator film provided on the single crystal semiconductor substrate in correspondence to the channel region; and a gate electrode provided on the gate insulator film in correspondence to the channel region with a predetermined gate length; wherein the channel region is defined by a back channel elimination region having an increased impurity concentration level exceeding the first impurity concentration level such that the back channel elimination region is located adjacent to the insulator substrate for eliminating the back channel effect, the back channel elimination region being provided under the gate electrode in a manner such that the back channel elimination region is separated from the source and the drain regions by a region having a smaller impurity concentration level.
    • 具有绝缘体上半导体结构的金属氧化物半导体器件包括绝缘体衬底; 设置在绝缘体基板上的单晶半导体基板,形成绝缘体上半导体结构的一部分的单晶半导体基板和绝缘基板; 掺杂到第一导电类型并限定在单晶半导体衬底中的源区和漏区; 在所述单晶半导体衬底中限定的沟道区域,以插入在所述源极和漏极区之间,所述沟道区被掺杂到具有第一杂质浓度水平的与所述第一导电类型相反的第二导电类型; 对应于所述沟道区设置在所述单晶半导体衬底上的栅绝缘膜; 以及栅极电极,设置在所述栅极绝缘膜上,对应于具有预定栅极长度的沟道区域; 其中沟道区由具有增加的杂质浓度水平超过第一杂质浓度水平的反向通道消除区限定,使得反向通道消除区位于绝缘体衬底附近以消除反向沟道效应,反向通道消除区 以栅极电极的方式设置为使得背沟道消除区域与源极和漏极区域分离具有较小杂质浓度水平的区域。
    • 30. 发明授权
    • Image forming apparatus
    • 图像形成装置
    • US08027607B2
    • 2011-09-27
    • US12366023
    • 2009-02-05
    • Munehito KurataDaizo FukuzawaMahito YoshiokaNoriaki SatoTooru ImaizumiKuniaki Kasuga
    • Munehito KurataDaizo FukuzawaMahito YoshiokaNoriaki SatoTooru ImaizumiKuniaki Kasuga
    • G03G15/20
    • G03G15/2042G03G2215/00413G03G2215/00772
    • The image forming apparatus, in the case where image forming is performed on a recording medium whose size covers a position of a second temperature detection element perpendicularly disposed to the recording medium conveyance direction, when the detected temperature rises to a predetermined temperature during execution of the first power supply control, a first power supply control is switched to a second power supply control. In the case where image forming is performed on a recording medium whose size does not cover a position of the second temperature detection element, when the detected temperature rises to a predetermined temperature during execution of the first power supply control, a conveyance control portion executes a control for extending the conveyance interval of the recording medium. Thus, an unduly large temperature rise in the non-sheet passing portion is prevented, and a good quality image can be provided without glossy unevenness in one sheet.
    • 在检测到的温度在执行期间检测到的温度上升到预定温度的情况下,在其尺寸覆盖垂直于记录介质输送方向的第二温度检测元件的位置的记录介质上进行图像形成的情况下, 第一电源控制,第一电源控制切换到第二电源控制。 在尺寸不覆盖第二温度检测元件的位置的记录介质上进行图像形成的情况下,当在第一电源控制执行期间检测到的温度上升到预定温度时,输送控制部分执行 用于延长记录介质的输送间隔的控制。 因此,防止非片材通过部分的过大的温度上升,并且可以在一张片材中没有光泽不均匀的情况下提供高质量的图像。