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21. 发明申请

US20140197377A1 CMOS NANOWIRE STRUCTURE 有权
标题翻译： CMOS纳米结构
公开(公告)号：US20140197377A1
公开(公告)日：2014-07-17
申请号：US13996503
申请日：2011-12-23
申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号： H01L29/06 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

22. 发明申请

US20140042386A1 NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS 有权
标题翻译：具有非离散源和排水区的纳米结构
公开(公告)号：US20140042386A1
公开(公告)日：2014-02-13
申请号：US13995930
申请日：2011-12-23
申请人： Stephen M. Cea , Annalisa Cappellani , Martin D. Giles , Rafael Rios , Seiyon Kim , Kelin J. Kuhn
发明人： Stephen M. Cea , Annalisa Cappellani , Martin D. Giles , Rafael Rios , Seiyon Kim , Kelin J. Kuhn
IPC分类号： H01L29/66
CPC分类号： H01L29/78618 , B82Y40/00 , H01L21/268 , H01L29/0673 , H01L29/0847 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66742 , H01L29/66787 , H01L29/66977 , H01L29/7839 , H01L29/7845 , H01L29/7848 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
摘要翻译：描述了具有非离散源极和漏极区域的纳米线结构。例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。每个纳米线包括设置在纳米线中的离散通道区域。栅电极堆叠围绕多个垂直堆叠的纳米线。一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

23. 发明申请

US20160049513A1 TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS 有权
标题翻译：用于非均匀应变半导体FINS的二维冷凝
公开(公告)号：US20160049513A1
公开(公告)日：2016-02-18
申请号：US14882440
申请日：2015-10-13
申请人： Jack T. Kavalieros , Nancy Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
发明人： Jack T. Kavalieros , Nancy Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165
CPC分类号： H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/66818 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
摘要翻译：公开了用于实现半导体翅片的多面冷凝的技术。这些技术可以用于例如制造基于鳍的晶体管。在一个示例的情况下，在体基板上设置应变层。应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

24. 发明申请

US20140285980A1 CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 有权
标题翻译：应变诱导缓冲器对电绝缘子的转换
公开(公告)号：US20140285980A1
公开(公告)日：2014-09-25
申请号：US13976068
申请日：2012-04-13
申请人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
发明人： Annalisa Cappellani , Van H. Le , Glenn A. Glass , Kelin J. Kuhn , Stephen M. Cea
IPC分类号： H01L29/06 , H01L21/02 , H05K1/18
CPC分类号： H01L29/66795 , H01L21/02233 , H01L21/02236 , H01L21/02238 , H01L21/02241 , H01L21/02255 , H01L21/02304 , H01L21/02439 , H01L21/0245 , H01L21/02455 , H01L21/02488 , H01L21/02532 , H01L21/306 , H01L21/76 , H01L21/7624 , H01L21/76283 , H01L29/0603 , H01L29/0642 , H01L29/0653 , H01L29/0657 , H01L29/1054 , H01L29/7378 , H01L29/785 , H01L33/12 , H05K1/18
摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
摘要翻译：公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些在应变诱导缓冲器上并具有埋入的电绝缘体层。例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

25. 发明申请

US20110147847A1 Methods and apparatus to reduce layout based strain variations in non-planar transistor structures 有权
标题翻译：减少非平面晶体管结构中基于布局的应变变化的方法和装置
公开(公告)号：US20110147847A1
公开(公告)日：2011-06-23
申请号：US12653971
申请日：2009-12-21
申请人： Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
发明人： Stephen M. Cea , Martin D. Giles , Kelin Kuhn , Jack T. Kavalieros , Markus Kuhn
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/785 , H01L21/76224 , H01L29/66795 , H01L29/7842
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

26. 发明申请

US20100163970A1 Trigate transistor having extended metal gate electrode 有权
标题翻译：用具有扩展金属栅电极的晶体管
公开(公告)号：US20100163970A1
公开(公告)日：2010-07-01
申请号：US12317966
申请日：2008-12-31
申请人： Titash Rakshit , Stephen M. Cea , Jack T. Kavalieros , Ravi Pillarisetty
发明人： Titash Rakshit , Stephen M. Cea , Jack T. Kavalieros , Ravi Pillarisetty
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.
摘要翻译：具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方。

27. 发明授权

US07473591B2 Transistor with strain-inducing structure in channel 有权
标题翻译：晶体管在通道中具有应变诱导结构
公开(公告)号：US07473591B2
公开(公告)日：2009-01-06
申请号：US11292428
申请日：2005-12-01
申请人： Stephen M. Cea , Ravindra Soman , Ramune Nagisetty , Sunit Tyagi , Sanjay Natarajan
发明人： Stephen M. Cea , Ravindra Soman , Ramune Nagisetty , Sunit Tyagi , Sanjay Natarajan
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/1054 , H01L29/7842
摘要： Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
摘要翻译：用于在器件的沟道区域中形成应变硅层的各种方法以及根据所公开的方法构造的器件。在一个实施例中，形成应变诱导层，在应变诱导层上形成松弛层，去除应变诱导层的一部分，这使得应变诱导层松弛并使应变放松层。

28. 发明授权

US06982433B2 Gate-induced strain for MOS performance improvement 有权
标题翻译：门诱导应变为MOS性能提高
公开(公告)号：US06982433B2
公开(公告)日：2006-01-03
申请号：US10459998
申请日：2003-06-12
申请人： Thomas Hoffman , Stephen M. Cea , Martin D. Giles
发明人： Thomas Hoffman , Stephen M. Cea , Martin D. Giles
IPC分类号： H01L29/06 , H01L31/007 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L21/823807 , H01L21/28044 , H01L29/1054 , H01L29/4925 , H01L29/7842 , H01L29/7845
摘要： There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.
摘要翻译：公开了一种装置，其包括限定该装置的内部的基板，包括栅电极的基板外部的装置，以及栅电极外部的应变层和基板的外部。

29. 发明授权

US08890120B2 Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS方法的隧道场效应晶体管（TFET）用于制造N型和P型TFET
公开(公告)号：US08890120B2
公开(公告)日：2014-11-18
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

30. 发明授权

US07781771B2 Bulk non-planar transistor having strained enhanced mobility and methods of fabrication 有权
标题翻译：具有应变增强的移动性和制造方法的散装非平面晶体管
公开(公告)号：US07781771B2
公开(公告)日：2010-08-24
申请号：US12025665
申请日：2008-02-04
申请人： Nick Lindert , Stephen M. Cea
发明人： Nick Lindert , Stephen M. Cea
IPC分类号： H01L29/06 , H01L29/10
CPC分类号： H01L29/7851 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7842 , H01L29/785 , H01L29/78687
摘要： A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：具有染色的增强迁移率的体三门极晶体管的方法及其制造方法。本发明是具有应变增强迁移率的非平面晶体管及其制造方法。晶体管具有形成在半导体衬底上的半导体本体，其中半导体本体在横向相对的侧壁上具有顶表面。半导体盖层形成在半导体本体的顶表面和侧壁上。在半导体本体的顶表面上的半导体覆盖层上形成栅介电层，并形成在半导体本体的侧壁上的覆盖层上。具有一对横向相对的侧壁的栅电极形成在栅介质层上和周围。在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

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