专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07971169B1 System and method for reducing the generation of inconsequential violations resulting from timing analyses 有权
标题翻译：用于减少由时序分析引起的无关紧要违规的产生的系统和方法
公开(公告)号：US07971169B1
公开(公告)日：2011-06-28
申请号：US12190784
申请日：2008-08-13
申请人： Alexander Y. Tetelbaum , Sreejit Chakravarty , Nicholas A. Callegari
发明人： Alexander Y. Tetelbaum , Sreejit Chakravarty , Nicholas A. Callegari
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation identifier configured to identify at least some timing violations in a circuit based on a timing analysis, (2) an unsensitizable path identifier configured to identify at least some unsensitizable paths in the circuit and (3) a repair list generator coupled to the timing violation identifier and the unsensitizable path identifier and configured to generate a repair list based on both the at least some timing violations and the at least some unsensitizable paths.
摘要翻译：一种减少由时序分析引起的无关紧要违规的产生的系统和方法，以及结合该系统或方法的电子设计自动化（EDA）工具。在一个实施例中，系统包括：（1）定时违规标识符，被配置为基于定时分析来识别电路中的至少一些定时违规，（2）未识别的路径标识符，被配置为识别电路中的至少一些不可识别的路径以及（3）修复列表生成器，其耦合到所述定时违反标识符和所述不可识别的路径标识符，并且被配置为基于所述至少一些定时违反和所述至少一些不可识别的路径来生成修复列表。

22. 发明授权

US07802159B1 Enhanced logic built-in self-test module and method of online system testing employing the same 有权
标题翻译：增强型逻辑内置自检模块和在线系统测试方法
公开(公告)号：US07802159B1
公开(公告)日：2010-09-21
申请号：US12170030
申请日：2008-07-09
申请人： Sreejit Chakravarty , Narendra Devta-Prasanna , Fan Yang
发明人： Sreejit Chakravarty , Narendra Devta-Prasanna , Fan Yang
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/318552
摘要： A logic built-in self-test (LBIST) module and a method of online system testing. In one embodiment, the LBIST module includes: (1) first and second data sources selectable to provide alternative respective first and second data to at least one scan chain and (2) a scan clock modifier associated with the first and second data sources and configured to drive the at least one scan chain with a selectively aperiodic modified scan clock signal.
摘要翻译：逻辑内置自检（LBIST）模块和在线系统测试方法。在一个实施例中，LBIST模块包括：（1）可选择的第一和第二数据源，以向至少一个扫描链提供备选的相应的第一和第二数据;以及（2）与第一和第二数据源相关联的扫描时钟修改器，以选择性地非周期性修改的扫描时钟信号来驱动所述至少一个扫描链。

23. 发明公开

US20240027516A1 TEST AND REPAIR OF INTERCONNECTS BETWEEN CHIPS 审中-公开
公开(公告)号：US20240027516A1
公开(公告)日：2024-01-25
申请号：US17871807
申请日：2022-07-22
申请人： Sreejit Chakravarty , Adithya Kashyap , Vijaya Chelli , Micha Shahar , Rakesh Kandula , Dovev Amosi
发明人： Sreejit Chakravarty , Adithya Kashyap , Vijaya Chelli , Micha Shahar , Rakesh Kandula , Dovev Amosi
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/2812 , G01R31/2853 , G01R31/31717
摘要： Embodiments herein relate to a test, repair, and diagnostic solution for chip-to-chip interconnects. In one aspect, on a first chip, a first finite state machine (FSM) is coupled to a set of transmit lanes. To test each transmit lane, one at a time, the first FSM is to apply a first periodic signal to a transmit lane under test and concurrently apply a second periodic signal to other transmit lanes of the set of transmit lanes, where a phase of the first periodic signal is opposite to a phase of the second periodic signal. A comparator compares a detected signal on the lane under test to an expected response. The comparator can be on the first chip, when the first chip is tested alone, or on a second chip, where the two chips are tested together.

24. 发明授权

US08656233B2 Scan cell designs with serial and parallel loading of test data 有权
标题翻译：使用串行和并行加载测试数据的扫描单元设计
公开(公告)号：US08656233B2
公开(公告)日：2014-02-18
申请号：US12982642
申请日：2010-12-30
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scan cell is configured to receive first, second and third data bits at respective first, second and third data inputs. A control input is configured to receive a control signal. Latching logic is configured to latch data received at the first and second latch inputs to a scan cell output. The first latch input is configured to receive the first data bit. Selection logic is configured to select between the second and third data bits depending on a state of the control signal, and to provide the selected bit to the second latch input.
摘要翻译：扫描单元被配置为在相应的第一，第二和第三数据输入端接收第一，第二和第三数据位。控制输入被配置为接收控制信号。锁存逻辑被配置为将在第一和第二锁存器输入处接收到的数据锁存到扫描单元输出。第一个锁存器输入被配置为接收第一个数据位。选择逻辑被配置为根据控制信号的状态在第二和第三数据位之间进行选择，并将选择的位提供给第二锁存器输入。

25. 发明申请

US20130258786A1 Victim Port-Based Design for Test Area Overhead Reduction in Multiport Latch-Based Memories 有权
标题翻译：基于端口的受阻器设计，用于多端口基于锁存的存储器中的测试区域开销降低
公开(公告)号：US20130258786A1
公开(公告)日：2013-10-03
申请号：US13431614
申请日：2012-03-27
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G11C7/10
CPC分类号： G11C29/50 , G11C7/1075 , G11C8/16 , G11C11/401 , G11C29/02 , G11C29/32 , G11C29/34
摘要： A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode associated with the latch-based memory device. The second multiplexer selectively provides output data from the plurality of first multiplexers to the input data register in the test mode, thereby providing a data path bypassing the latch array in the test mode. Embodiments of a corresponding method and computer-readable medium are also provided.
摘要翻译：多端口基于锁存器的存储器件包括锁存器阵列，多个第一复用器和第二多路复用器。锁存器阵列以与基于锁存器的存储器件相关联的功能模式响应来自输入数据寄存器的输出数据。多个第一多路复用器在功能模式下响应来自锁存器阵列的输出数据。多个第一多路复用器响应于与基于锁存器的存储器件相关联的测试模式中的来自输入数据寄存器的输出数据。第二复用器在测试模式中选择性地将多个第一多路复用器的输出数据提供给输入数据寄存器，从而在测试模式下提供绕过锁存器阵列的数据路径。还提供了相应方法和计算机可读介质的实施例。

26. 发明申请

US20130111285A1 SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MULTIPLEXING 审中-公开
标题翻译：具有功能输出多路复用的扫描电路扫描电路
公开(公告)号：US20130111285A1
公开(公告)日：2013-05-02
申请号：US13283070
申请日：2011-10-27
申请人： Sreejit Chakravarty , Cam Luong Lu
发明人： Sreejit Chakravarty , Cam Luong Lu
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises multiplexing circuitry configured to select one of multiple data lines of the scan cell for application to a functional output of the scan cell. For example, the multiplexing circuitry may comprise an output multiplexer configured to select between data outputs of master and slave flip-flops for connection to the functional output of the scan cell responsive to a test mode select.
摘要翻译：集成电路包括扫描测试电路和经受使用扫描测试电路的测试的附加电路。扫描测试电路包括具有多个扫描单元的至少一个扫描链，其中扫描链被配置为以扫描移动模式运行作为串行移位寄存器，并从附加的至少一部分中捕获功能数据功能运行模式下的电路。至少扫描链的一个扫描单元中的一个包括多路复用电路，该多路复用电路经配置以选择扫描单元的多条数据线之一，以应用于扫描单元的功能输出。例如，复用电路可以包括输出多路复用器，其被配置为响应于测试模式选择在主触发器和从属触发器的数据输出之间进行选择，以连接到扫描单元的功能输出。

27. 发明授权

US08228750B2 Low cost comparator design for memory BIST 失效
标题翻译：低成本比较器设计用于存储器BIST
公开(公告)号：US08228750B2
公开(公告)日：2012-07-24
申请号：US12879110
申请日：2010-09-10
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , Y10T29/41
摘要： A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector.
摘要翻译：比较器确定从被测存储器接收的响应向量的保真度。比较器包括第一逻辑门，其被配置为输出作为响应向量的位的第一正确子集的逻辑或的第一值。第二逻辑门被配置为输出第二个值，该第二值是正确的位子集的逻辑NAND。第一多路复用器被配置为基于对应于响应向量的校验向量的第一比特的值在第一和第二值之间进行选择。

28. 发明申请

US20120179946A1 LOGIC BIST FOR SYSTEM TESTING USING STORED PATTERNS 有权
标题翻译：使用存储模式进行系统测试的逻辑BIST
公开(公告)号：US20120179946A1
公开(公告)日：2012-07-12
申请号：US12985604
申请日：2011-01-06
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G06F11/27
CPC分类号： G01R31/318544
摘要： A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test.
摘要翻译：存储模式逻辑自检系统包括存储器，被测器件和测试控制器。存储器存储测试模式数据，包括测试刺激。被测设备包括扫描链和可配置为控制扫描链的操作的测试访问端口。测试控制器被配置为通过控制存储器来测试被测设备，以将测试刺激输出到被测器件。测试控制器控制测试访问端口将测试刺激加载到扫描链中，并从被测设备接收并评估响应数据。

29. 发明申请

US20120173939A1 SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA 有权
标题翻译：具有串行和并行加载测试数据的扫描单元设计
公开(公告)号：US20120173939A1
公开(公告)日：2012-07-05
申请号：US12982642
申请日：2010-12-30
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： A scan cell is configured to receive first, second and third data bits at respective first, second and third data inputs. A control input is configured to receive a control signal. Latching logic is configured to latch data received at the first and second latch inputs to a scan cell output. The first latch input is configured to receive the first data bit. Selection logic is configured to select between the second and third data bits depending on a state of the control signal, and to provide the selected bit to the second latch input.
摘要翻译：扫描单元被配置为在相应的第一，第二和第三数据输入端接收第一，第二和第三数据位。控制输入被配置为接收控制信号。锁存逻辑被配置为将在第一和第二锁存器输入处接收到的数据锁存到扫描单元输出。第一个锁存器输入被配置为接收第一个数据位。选择逻辑被配置为根据控制信号的状态在第二和第三数据位之间进行选择，并将选择的位提供给第二锁存器输入。

30. 发明授权

US08191029B2 Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing 失效
标题翻译：定时误差采样发生器，集成电路保持和设置违规的关键路径监视器和定时测试方法
公开(公告)号：US08191029B2
公开(公告)日：2012-05-29
申请号：US12334403
申请日：2008-12-12
申请人： Alexander Tetelbaum , Sreejit Chakravarty
发明人： Alexander Tetelbaum , Sreejit Chakravarty
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.
摘要翻译：定时误差采样发生器，路径监视器，IC，执行定时测试的方法和单元库。在一个实施例中，定时误差采样发生器包括：（1）具有输入和输出的保持延迟元件，并且被配置为通过向在所述输入处接收到的时钟信号提供第一预定延迟来在所述输出处提供保持违反延迟信号，所述第一预定延迟对应于要被监视的路径的保持违规时间;以及（2）具有耦合到所述保持延迟元件的所述输入的第一输入的保持逻辑元件，耦合到所述保持延迟的所述输出的第二输入元件和所述保持逻辑元件被配置为响应于所述第一和第二输入以在所述第一和第二输入处的逻辑电平处于相同电平时提供时钟保持信号的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式