专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07549059B2 Transferring data values via a data bus or storing data values using a selectable representation 有权
公开(公告)号：US07549059B2
公开(公告)日：2009-06-16
申请号：US10179020
申请日：2002-06-26
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G06F11/30
CPC分类号： H04L12/417
摘要： Data values being stored and transferred within a data processing system 8 have a selectable representation, such as true and complement, as indicated by an accompanying representation specifying bit. This assists in obscuring the operation and the power signature of the device in a manner that improves security.

22. 发明授权

US5875465A Cache control circuit having a pseudo random address generator 失效
标题翻译：高速缓存控制电路具有伪随机地址发生器
公开(公告)号：US5875465A
公开(公告)日：1999-02-23
申请号：US832091
申请日：1997-04-03
申请人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
发明人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/128 , G06F12/0848 , G06F12/126
摘要： A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.
摘要翻译：一种包含高速缓冲存储器2和中央处理单元的数据处理系统。存储控制电路10响应于可编程分区设置PartVal，以根据中央处理单元4是否用信号I / D指示要存储在高速缓存存储器2中的单词来指示高速缓存在指令字和数据字之间由指令字缓存未命中或数据字高速缓存未命中引起。缓存存储器阵列2可以具有可编程尺寸的部分锁定，使得它不被替换。在进行重写的互补可编程范围内的选择使用伪随机数选择技术，该伪随机数生成器以线性反馈移位寄存器的形式触发递增计数器。

23. 发明授权

US5675615A Apparatus and method for switching asynchronous clock signals 失效
标题翻译：用于切换异步时钟信号的装置和方法
公开(公告)号：US5675615A
公开(公告)日：1997-10-07
申请号：US744121
申请日：1996-11-05
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G06F1/06 , G06F1/08 , H04L7/00
CPC分类号： G06F1/08
摘要： Within a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.
摘要翻译：在具有不同频率（fclk，mclk）的两个备选时钟信号的数据处理系统中，有必要提供一种在时钟信号之间切换的机制。当从快速时钟（fclk）切换到慢时钟（mclk）时，系统在与决定是否更改时钟的决定相关的处理延迟（PD）之后采用来自第一个下降沿（ffe）的慢时钟。该处理延迟可以大于快速时钟周期的一半。相反，当从慢时钟切换到快时钟时，系统采用跟随处理延迟的第一个上升沿（频率）的快速时钟。因此，提供了一种系统，其中根据时钟信号的改变方向采用不同的同步策略。

24. 发明申请

US20090235092A1 Transferring data values via a data bus or storing data values using a selectable representation 有权
标题翻译：通过数据总线传输数据值或使用可选择的表示存储数据值
公开(公告)号：US20090235092A1
公开(公告)日：2009-09-17
申请号：US12453219
申请日：2009-05-01
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G06F11/30
CPC分类号： H04L12/417
摘要： Data values being stored and transferred within a data processing system 8 have a selectable representation, such as true and complement, as indicated by an accompanying representation specifying bit. This assists in obscuring the operation and the power signature of the device in a manner that improves security.
摘要翻译：在数据处理系统8内存储和传送的数据值具有如伴随的表示指定位所指示的可选表示，例如真和补。这有助于以提高安全性的方式掩盖设备的操作和功能签名。

25. 发明授权

US07340573B2 Apparatus and method for controlling access to a memory unit 有权
标题翻译：用于控制对存储器单元的访问的装置和方法
公开(公告)号：US07340573B2
公开(公告)日：2008-03-04
申请号：US10714481
申请日：2003-11-17
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G06F12/00
CPC分类号： G06F12/1491 , G06F12/0802
摘要： The present invention provides a data processing apparatus and method for controlling access to a memory unit. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory unit is also provided that comprises a plurality of entries and is operable to store data required by the processor. Each entry is operable to store one or more data items consisting of either secure data or non-secure data, and a flag is associated with each entry in the memory unit to store a value indicating whether the one or more data items stored in the associated entry are secure data or non-secure data. When the processor is operating in the at least one non-secure mode, the memory unit is operable, upon receipt of a memory access request issued by the processor when access to an item of data is required, to prevent access to any data item within an entry of the memory unit that the associated flag indicates has secure data stored therein.
摘要翻译：本发明提供一种用于控制对存储器单元的访问的数据处理装置和方法。数据处理装置包括可以多个模式操作的处理器和多个域，所述多个域包括安全域和非安全域，所述多个模式包括至少一个非安全模式，非安全域和至少一个安全模式是安全域中的模式。处理器是可操作的，使得当以安全模式执行程序时，程序可以访问当处理器以非安全模式操作时不可访问的安全数据。还提供了一种存储单元，其包括多个条目并且可操作以存储处理器所需的数据。每个条目可操作以存储由安全数据或非安全数据组成的一个或多个数据项，并且标志与存储器单元中的每个条目相关联，以存储指示存储在相关联中的一个或多个数据项的值条目是安全数据或非安全数据。当处理器以至少一个非安全模式操作时，存储器单元可操作地在接收到需要访问数据项时由处理器发出的存储器访问请求，以防止访问任何数据项关联标志指示的存储单元的条目具有存储在其中的安全数据。

26. 发明授权

US06272033B1 Status bits for cache memory 有权
标题翻译：高速缓存的状态位
公开(公告)号：US06272033B1
公开(公告)日：2001-08-07
申请号：US09512329
申请日：2000-02-24
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G06F12/0802 , G06F12/0891 , G11C15/04
摘要： Data processing apparatuses provided comprising a memory operable to store a plurality of data words, each data word being associated with at least one status bit giving information regarding a status of said data word; a status bit store operable to store said status bits within a hierarchical relationship such that a combined status relating to a plurality of first level status bits at a first level within said hierarchical relationship is indicated by a second level status bit at a second level within said hierarchical relationship, said second level being higher in said hierarchical relationship than said first level; and status querying logic operative to determine a status of a data word within said memory by examining status bits within said status bit store starting at a top level within said hierarchical relationship and working down through said hierarchical relationship until a status bit is reached that indicates said status of said data word independently of any status bits lower in said hierarchical relationship. In this way a global or large-scale change to status bits may be made by modifying relatively few higher level status bits within the hierarchical relationship thereby achieving a high speed change with reduced levels of special purpose hardware being required.
摘要翻译：提供的数据处理装置包括可操作以存储多个数据字的存储器，每个数据字与至少一个提供关于所述数据字状态的信息的状态位相关联; 状态位存储器，用于将所述状态位存储在分级关系中，使得与所述分级关系中的第一级的多个第一级状态位有关的组合状态由所述分层关系中的第二级的第二级状态位指示所述第二级别在所述层级关系中高于所述第一级别; 以及状态查询逻辑，用于通过从所述层级关系中的顶层开始检查所述状态位存储中的状态位，并通过所述分级关系来确定所述存储器内的数据字的状态，直到达到表示所述层级关系的状态位所述数据字的状态与所述分级关系中的任何状态位无关。以这种方式，可以通过修改分层关系内的相对较少的较高级别的状态位来进行对状态位的全局或大规模改变，从而实现需要降低专用硬件水平的高速变化。

27. 发明授权

US5802598A Data memory access control and method using fixed size memory sections that are sub-divided into a fixed number of variable size sub-sections 失效
标题翻译：数据存储器访问控制和使用固定大小的存储器部分的方法，其被细分为固定数量的可变大小子部分
公开(公告)号：US5802598A
公开(公告)日：1998-09-01
申请号：US538291
申请日：1995-10-02
申请人： Simon Charles Watt
发明人： Simon Charles Watt
IPC分类号： G06F12/02 , G06F12/14 , G06F12/00
CPC分类号： G06F12/0292
摘要： A data processing system and method include an address space which is controlled by a memory management unit and which is treated as being divided into main-sections (chunks) and sub-sections (grains). The grains may be configured to be of one of a selected number of sizes. Irrespective of the grain size, there is a fixed number of grains within each chunk. A bank of grain registers 20 stores access control parameters for each grain. In operation, a memory address (va�31:0!) is decoded to determine which chunk it relates to so that the grain size for that chunk may be determined. Having determined the grain size, the rest of the address may be decoded to pick out the grain in which the address is located, and then the access control parameters for that grain are recovered.
摘要翻译：数据处理系统和方法包括由存储器管理单元控制并被分为主要部分（块）和子部分（颗粒））的地址空间。颗粒可以被配置为选定数量的尺寸之一。不管颗粒大小，每个块内都有固定数量的颗粒。一批谷物寄存器20存储每个谷物的访问控制参数。在操作中，对存储器地址（va [31：0]）进行解码以确定其相关的块，从而可以确定该块的粒度。确定了粒度后，地址的其余部分可以被解码以拾取地址所在的粒度，然后恢复该粒度的访问控制参数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式