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21. 发明授权

US08903000B2 Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor 有权
标题翻译：传输电路，接收电路，传输方法，接收方法，通信系统及其通信方法
公开(公告)号：US08903000B2
公开(公告)日：2014-12-02
申请号：US13823575
申请日：2011-09-30
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04B1/52
CPC分类号： H04L7/10 , H04L1/0057 , H04L1/0083 , H04L25/4908 , H04W56/00
摘要： In transmission of channel-coded serial data, early establishment of symbol synchronization between a transmitter and a receiver is achieved while reducing coding loss in transmission of valid data. In an idle period for not transmitting the valid data, a transmitting circuit selects first channel coding (e.g. 8B/10B coding) enabling early establishment of synchronization and transmits a synchronization symbol encoded using the first channel coding. In response to this, a receiving circuit establishes and maintains symbol synchronization. When the valid data is transmitted, the transmitting circuit transmits a symbol indicating a packet start position, selects second channel coding (e.g. 64B/66B coding) having less coding loss than the first channel coding, and transmits the valid data encoded using the second channel coding. Upon reception of the symbol indicating the packet start position, the receiving circuit switches to reception using the second channel coding and receives the valid data.
摘要翻译：在传输信道编码的串行数据时，实现了发射机和接收机之间的符号同步的早期建立，同时减少了传输有效数据时的编码丢失。在不发送有效数据的空闲时段中，发送电路选择能够提前建立同步的第一信道编码（例如8B / 10B编码），并发送使用第一信道编码编码的同步符号。响应于此，接收电路建立并维持符号同步。当发送有效数据时，发送电路发送表示分组开始位置的符号，选择比第一信道编码更少的编码丢失的第二信道编码（例如64B / 66B编码），并发送使用第二信道编码的有效数据编码。在接收到指示分组开始位置的符号时，接收电路使用第二信道编码切换到接收，并接收有效数据。

22. 发明授权

US08214662B2 Multiprocessor control unit, control method performed by the same, and integrated circuit 有权
标题翻译：多处理器控制单元，由其执行的控制方法和集成电路
公开(公告)号：US08214662B2
公开(公告)日：2012-07-03
申请号：US12377938
申请日：2008-03-13
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G06F1/00 , G06F9/46
CPC分类号： G06F1/3203 , G06F9/5094 , G06F9/52 , G06F11/3423 , G06F11/348 , Y02D10/22 , Y02D10/34
摘要： A multiprocessor control unit acquires first non processing time information on a first non processing time represented for each processor, wherein the first non processing time represents a time in which a first block is not executed in a first barrier establishment time from barrier synchronization start until barrier synchronization establishment of the first program block, and acquires second non processing time information on a second non processing time represented for each processor, wherein the second non processing time represents a time in which a second block is not processed in a second barrier establishment time from barrier synchronization start until barrier synchronization establishment of the second program block. The multiprocessor control unit controls a power supply for the processors while the first and second program blocks are consecutively executed in parallel, using the first and second non processing time information acquired.
摘要翻译：多处理器控制单元获取关于每个处理器表示的第一非处理时间的第一非处理时间信息，其中第一非处理时间表示在从屏障同步开始直到屏障的第一屏障建立时间内不执行第一块的时间同步建立第一程序块，并且获取关于为每个处理器表示的第二非处理时间的第二非处理时间信息，其中第二非处理时间表示在第二个屏障建立时间内没有处理第二个块的时间屏障同步开始直到第二程序块的屏障同步建立。多处理器控制单元使用所获取的第一和第二非处理时间信息来并行地连续执行第一和第二程序块时，控制处理器的电源。

23. 发明申请

US20120120960A1 NODE DEVICE, INTEGRATED CIRCUIT AND CONTROL METHOD IN RING TRANSMISSION SYSTEM 有权
标题翻译：节点设备，集成电路和控制方法在传输系统中的应用
公开(公告)号：US20120120960A1
公开(公告)日：2012-05-17
申请号：US13386756
申请日：2011-05-24
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04L12/56 , H04L12/427
CPC分类号： H04L12/437 , H04L12/40013
摘要： A node device in a ring transmission system in which a plurality of node devices are connected as a ring via serial links has a PHY transitioning between a normal mode and a loopback mode with timing that maintains symbol lock between an idle frame transmitted to a later serial link in the normal mode according a transmission instruction, and an idle frame from an earlier node device looped back for output to a later serial link during the loopback mode, thus performing relay processing on non-locally addressed data packets during the loopback mode.
摘要翻译：通过串行链路将多个节点设备作为环路连接的环形传输系统中的节点设备具有正常模式和环回模式之间的PHY转换，其中定时保持发送到后续串行的空闲帧之间的符号锁定在回送模式期间，根据传输指令以及来自较早节点设备的空闲帧循环输出到稍后的串行链路，从而在环回模式期间对非本地寻址的数据分组执行中继处理。

24. 发明申请

US20110141898A1 COMMUNICATION SYSTEM, COMMUNICATION DEVICE, INTEGRATED CIRCUIT, AND COMMUNICATION METHOD 有权
标题翻译：通信系统，通信设备，集成电路和通信方法
公开(公告)号：US20110141898A1
公开(公告)日：2011-06-16
申请号：US13059263
申请日：2010-03-17
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L12/42 , H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A communication system includes communication devices that are connected with one another in a ring via a serial link. In the communication system, one communication device issues a standby packet for causing each communication device connected to a part of the link that is not involved with data transfer to switch to standby mode. Each communication device connected to this part of the link relays the standby packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the standby packet, causes the own device to switch to standby mode. Further, a communication device that performs communication with said one communication device issues a loopback packet for causing each communication device connected to a part of the link that is involved with data transfer to switch to loopback mode. Each communication device connected to this part of the link relays the loopback packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the loopback packet, causes the own device to switch to loopback mode.
摘要翻译：通信系统包括通过串行链路在环中彼此连接的通信设备。在通信系统中，一个通信设备发出备用分组，使得连接到不涉及数据传输的链路的一部分的每个通信设备切换到待机模式。连接到链路的这一部分的每个通信设备将链路中的紧接在前的通信设备的备用分组中继到链路中紧接着的通信设备，并且在中继备用分组之后，使得自己的设备切换到待机模式。此外，与所述一个通信设备进行通信的通信设备发出环回分组，使得连接到涉及数据传输的链路的一部分的每个通信设备切换到环回模式。与链路的这一部分连接的每个通信装置将链路中的紧急通信装置的环回分组中继到链路中的紧随其后的通信装置，并且在中继环回分组之后，使得本装置切换到环回模式。

25. 发明申请

US20100153761A1 MULTIPROCESSOR CONTROL UNIT, CONTROL METHOD PERFORMED BY THE SAME, AND INTEGRATED CIRCUIT 有权
标题翻译：多处理器控制单元，由其执行的控制方法和集成电路
公开(公告)号：US20100153761A1
公开(公告)日：2010-06-17
申请号：US12377938
申请日：2008-03-13
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G06F1/32 , G06F1/26 , G06F9/52
CPC分类号： G06F1/3203 , G06F9/5094 , G06F9/52 , G06F11/3423 , G06F11/348 , Y02D10/22 , Y02D10/34
摘要： A multiprocessor control unit according to the present invention comprises acquisition means for acquiring first non processing time information on a first non processing time represented for each processor, wherein the first non processing time represents a time in which a first block is not executed in a first barrier establish time from barrier synchronization start until barrier synchronization establishment of the first program block, and acquiring second non processing time information on a second non processing time represented for each processor, wherein the second non processing time represents a time in which a second block is not processed in a second barrier establish time from barrier synchronization start until barrier synchronization establishment of the second program block; and power control means for controlling power supply to the plurality of processors while the first and second program blocks are consecutively executed in parallel, using the first and second non processing time information acquired by the acquisition means.
摘要翻译：根据本发明的多处理器控制单元包括获取装置，用于在为每个处理器表示的第一非处理时间上获取第一非处理时间信息，其中第一非处理时间表示在第一非处理时间信息中第一个块未被执行的时间屏障建立从屏障同步开始到屏障同步建立第一程序块的时间，以及在为每个处理器表示的第二非处理时间上获取第二非处理时间信息，其中第二非处理时间表示第二块处于没有在第二屏障中处理建立时间，从屏障同步开始到第二程序块的屏障同步建立; 以及功率控制装置，用于在使用由获取装置获取的第一和第二非处理时间信息的同时并行地连续执行第一和第二程序块的同时控制对多个处理器的供电。

26. 发明授权

US07398403B2 Multiprocessor control apparatus, control method thereof, and integrated circuit 有权
标题翻译：多处理器控制装置，其控制方法和集成电路
公开(公告)号：US07398403B2
公开(公告)日：2008-07-08
申请号：US11169026
申请日：2005-06-27
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228
摘要： Provided is a multiprocessor control apparatus that restrains impairment of processing speed of entire operations, while pursuing power consumption saving for a multiprocessor. The multiprocessor control apparatus has: an execution control unit operable to control a processor to, when processors other than the processor have ended respective operations performed in parallel, start performing an operation that uses a result of the operations; and a power control unit operable to control power supply to the processor, where when the processor has been under power-supply restriction, the power control unit cancels the power-supply restriction before one of the other processors, which is the last of all the other processors to end a corresponding operation, ends the corresponding operation.
摘要翻译：提供了一种多处理器控制装置，其抑制整个操作的处理速度的损害，同时为多处理器寻求功耗节省。多处理器控制装置具有：执行控制单元，用于控制处理器，当处理器之外的处理器已经结束并行执行的各个操作时，开始执行使用操作结果的操作; 以及功率控制单元，其可操作以控制对所述处理器的电力供应，其中当所述处理器处于电源限制状态时，所述功率控制单元在所有其他处理器中的最后一个处理器之前取消所述电源限制其他处理器结束相应的操作，结束相应的操作。

27. 发明授权

US5327260A Image processing apparatus for smoothing edges of image 失效
标题翻译：用于平滑图像边缘的图像处理装置
公开(公告)号：US5327260A
公开(公告)日：1994-07-05
申请号：US980964
申请日：1992-11-24
申请人： Mutsuo Shimomae , Masayoshi Watanuki , Shinichiro Nishioka
发明人： Mutsuo Shimomae , Masayoshi Watanuki , Shinichiro Nishioka
IPC分类号： B41J2/44 , B41J2/485 , G06K15/12 , H04N1/409 , H04N1/417 , H04N1/40
CPC分类号： G06K15/1223
摘要： An image processing system for smoothing edges of an image, includes a sampling part for sampling a group of dots from an image having a plurality of input black and white dots, the group of dots having a target dot at the center of a region and being sampled for each dot of the image, a recognition part for recognizing a dot pattern from the sampled dots, the dot pattern described by successive black dots and located at a boundary between a black dot region and a white dot region, and for producing code signals from the result of the recognition to define features of the dot pattern for each target dot, a discrimination part for detecting whether or not each target dot is part of an inclined line having a gradient relative to horizontal or vertical direction in response to the code signals, thus determining whether or not each target dot is to be corrected, a correction part with a memory, for inputting the code signals to the memory as address inputs when the dot is to be corrected, and for outputting a corresponding correction dot data from the memory in accordance with the code signals, and an output part for outputting an image with corrected dots which are in accordance with the correction dot data of the correction part.
摘要翻译：一种用于平滑图像边缘的图像处理系统，包括：采样部分，用于从具有多个输入黑白点的图像中采样一组点，所述一组点在一个区域的中心具有目标点，并且是对于图像的每个点进行采样，用于从采样点识别点图案的识别部分，由连续的黑点描述并位于黑点区域和白点区域之间的边界处的点图案，以及用于产生代码信号从识别结果来定义每个目标点的点图案的特征;判别部分，用于根据代码信号检测每个目标点是否相对于水平或垂直方向具有梯度的倾斜线的一部分，从而确定是否要校正每个目标点，具有存储器的校正部分，用于当要校正点时将代码信号输入到存储器作为地址输入，并且用于根据代码信号从存储器输出相应的校正点数据;以及输出部分，用于输出具有校正点的与修正部分的校正点数据相符的图像。

28. 发明授权

US08713231B2 Interface circuit and interface system 有权
标题翻译：接口电路和接口系统
公开(公告)号：US08713231B2
公开(公告)日：2014-04-29
申请号：US13139397
申请日：2010-11-01
申请人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
发明人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译：为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。在差分信号接收电路被激活之后，由内置控制器维持有效状态。因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在意想不到的时间降到了低水平。

29. 发明申请

US20130332504A1 STATION, TARGET APPARATUS, INITIATOR APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD 有权
标题翻译：台站，目标装置，发射机装置，通信系统和通信方法
公开(公告)号：US20130332504A1
公开(公告)日：2013-12-12
申请号：US13985999
申请日：2012-03-09
申请人： Shinichiro Nishioka , Yuusaku Ohta , Kozo Nishimura
发明人： Shinichiro Nishioka , Yuusaku Ohta , Kozo Nishimura
IPC分类号： H04L29/08
CPC分类号： H04L67/288 , H04L41/0846 , H04L41/0853 , H04L67/2842 , H04N21/6371
摘要： A plurality of networks each having a host are connected to achieve a transparent transaction between devices belonging to the different networks. A target apparatus includes a station and a host. In response to a get device handle request from an initiator apparatus, the station acquires, from the host, configuration information of a target device and relays transactions between the initiator apparatus and the target device, without requiring involvement of the host.
摘要翻译：每个具有主机的多个网络被连接以实现属于不同网络的设备之间的透明事务。目标设备包括站和主机。响应于来自发起者设备的获取设备处理请求，站从主机获取目标设备的配置信息，并且中继启动器设备和目标设备之间的事务，而不需要主机的参与。

30. 发明申请

US20130315250A1 TRANSFER CONTROL DEVICE, INTEGRATED CIRCUIT THEREOF, TRANSFER CONTROL METHOD, AND TRANSFER CONTROL SYSTEM 有权
标题翻译：传输控制装置，其集成电路，传输控制方法和传送控制系统
公开(公告)号：US20130315250A1
公开(公告)日：2013-11-28
申请号：US13984928
申请日：2012-01-27
申请人： Yuusaku Ohta , Shinichiro Nishioka
发明人： Yuusaku Ohta , Shinichiro Nishioka
IPC分类号： H04L12/741
CPC分类号： H04L45/74 , H04L12/4625 , H04L12/6418 , H04L61/2038
摘要： To achieve efficient data transfer between a first network 1 and a second network 2, and, in particular, to reduce processing load pertaining to address conversion, a transfer control device 110 in the first network 1 acquires an address of a transfer target device 240 in the second network 2, and assigns the acquired address to a transfer device 140 in the first network. When data transmitted through the first network 1 is to be transferred to the transfer target device 240 via the transfer device 140, there is no need to perform address conversion as the transfer device 140 and the transfer target device 240 are assigned the same address.
摘要翻译：为了实现第一网络1和第二网络2之间的有效数据传输，并且特别地，为了减少与地址转换有关的处理负担，第一网络1中的传输控制设备110获取传输目标设备240的地址第二网络2，并且将获取的地址分配给第一网络中的传送设备140。当通过第一网络1发送的数据将经由传送装置140传送到转移目标装置240时，不需要执行地址转换，因为传送装置140和传送目标装置240被分配相同的地址。

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