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21. 发明申请

US20130130157A1 METHOD FOR MANUFACTURING PHOTO MASK, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROGRAM 有权
标题翻译：制造摄影胶片的方法，制造半导体器件的方法和程序
公开(公告)号：US20130130157A1
公开(公告)日：2013-05-23
申请号：US13679396
申请日：2012-11-16
申请人： Akiko Mimotogi , Suigen Kyoh , Tetsuro Nakasugi
发明人： Akiko Mimotogi , Suigen Kyoh , Tetsuro Nakasugi
IPC分类号： G03F1/62
CPC分类号： G03F1/62
摘要： According to one embodiment, a method for manufacturing a photo mask, includes acquiring first data on respective shapes of a plurality of mask substrates, acquiring second data on respective shapes of a plurality of pellicles, and determining a combination of the mask substrate and the pellicle based on the first data and the second data.
摘要翻译：根据一个实施例，一种制造光掩模的方法包括：获取关于多个掩模基板的各个形状的第一数据，获取关于多个防护薄膜的各自形状的第二数据，以及确定掩模基板和防护薄膜组件的组合基于第一数据和第二数据。

22. 发明授权

US08118585B2 Pattern formation method and a method for manufacturing a semiconductor device 有权
标题翻译：图案形成方法及半导体装置的制造方法
公开(公告)号：US08118585B2
公开(公告)日：2012-02-21
申请号：US12882944
申请日：2010-09-15
申请人： Masayuki Hatano , Suigen Kyoh , Tetsuro Nakasugi
发明人： Masayuki Hatano , Suigen Kyoh , Tetsuro Nakasugi
IPC分类号： A01J21/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , G03F9/00
摘要： In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern.
摘要翻译：在一个实施例中，公开了图案形成方法。该方法可以将液态树脂材料放置在工件基板上。该方法可以将模板压靠树脂材料并测量模板的突起的下表面与工件基板的上表面之间的距离。模板包括图案形成区域和围绕图案形成区域的周边区域。在图案形成区域中形成用于电路图案形成的图案，并且在周向区域中形成突起。该方法可以通过在压制模板的状态下固化树脂材料来形成树脂图案。此外，该方法可以将模板与树脂图案分离。

23. 发明申请

US20090306805A1 SEMICONDUCTOR DEVICE PRODUCTION CONTROL METHOD 有权
标题翻译：半导体器件生产控制方法
公开(公告)号：US20090306805A1
公开(公告)日：2009-12-10
申请号：US12480355
申请日：2009-06-08
申请人： Suigen Kyoh
发明人： Suigen Kyoh
IPC分类号： G06F17/00 , H01L21/66
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device production control method includes monitoring, after a production process of a semiconductor device, a process result at a predetermined position of a pattern to which the process is applied, to obtain a deviation with respect to a predetermined target result, quantitatively obtaining a degree of influence on an operation of a semiconductor device from the deviation of the process result, and comparing the degree of influence that is quantitatively obtained with a predetermined allowable margin for operation specifications of the semiconductor device.
摘要翻译：半导体器件制造控制方法包括在半导体器件的制造处理之后，在施加了该工艺的图案的预定位置处监视处理结果，以获得相对于预定目标结果的偏差，定量获得根据处理结果的偏差对半导体器件的操作产生的影响程度，并将定量获得的影响程度与半导体器件的操作规范的预定允许余量进行比较。

24. 发明授权

US07539962B2 Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device 失效
标题翻译：图案数据校正方法，光掩模制造方法，半导体器件制造方法，程序和半导体器件
公开(公告)号：US07539962B2
公开(公告)日：2009-05-26
申请号：US11219813
申请日：2005-09-07
申请人： Suigen Kyoh
发明人： Suigen Kyoh
IPC分类号： G06F17/50 , H01L23/00
CPC分类号： G06F17/5081
摘要： There is provided a method of correcting pattern data for a semiconductor device, including acquiring pattern data for a lower layer, pattern data for an upper layer, and pattern data for a connecting layer containing connecting patterns to connect patterns contained in the lower layer and patterns contained in the upper layer, grouping patterns contained in the lower layer, the upper layer, and the connecting layer into a plurality of groups in which patterns in the same group are to be set at the same electric potential, acquiring a first distance between one edge of one connecting pattern contained in one group and an edge of a pattern contained in another group, and moving the one edge in a direction in which a size of the one connecting pattern increases, based on the first distance.
摘要翻译：提供了一种校正半导体器件的图案数据的方法，包括获取下层的图案数据，上层的图案数据和用于连接图案的连接层的图案数据，以连接包含在下层中的图案和图案包含在上层中，将包含在下层，上层和连接层中的图案分组成多个组，其中将同一组中的图案设置在相同的电位，获取一个包含在一组中的一个连接图案的边缘和包含在另一组中的图案的边缘，并且基于第一距离沿着一个连接图案的尺寸增大的方向移动该一个边缘。

25. 发明申请

US20050235245A1 Design pattern correction method and mask pattern producing method 有权
标题翻译：设计图案校正方法和掩模图案制作方法
公开(公告)号：US20050235245A1
公开(公告)日：2005-10-20
申请号：US11012613
申请日：2004-12-16
申请人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
发明人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/00 , H01L21/027 , H01L21/82
CPC分类号： G06F17/5081
摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
摘要翻译：公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

26. 发明授权

US08285412B2 Semiconductor device production control method 有权
标题翻译：半导体器件生产控制方法
公开(公告)号：US08285412B2
公开(公告)日：2012-10-09
申请号：US12480355
申请日：2009-06-08
申请人： Suigen Kyoh
发明人： Suigen Kyoh
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device production control method includes monitoring, after a production process of a semiconductor device, a process result at a predetermined position of a pattern to which the process is applied, to obtain a deviation with respect to a predetermined target result, quantitatively obtaining a degree of influence on an operation of a semiconductor device from the deviation of the process result, and comparing the degree of influence that is quantitatively obtained with a predetermined allowable margin for operation specifications of the semiconductor device.
摘要翻译：半导体器件制造控制方法包括在半导体器件的制造处理之后，在施加了该工艺的图案的预定位置处监视处理结果，以获得相对于预定目标结果的偏差，定量获得根据处理结果的偏差对半导体器件的操作产生的影响程度，并将定量获得的影响程度与半导体器件的操作规范的预定允许余量进行比较。

27. 发明授权

US08230379B2 Layout generating method for semiconductor integrated circuits 失效
标题翻译：半导体集成电路布局生成方法
公开(公告)号：US08230379B2
公开(公告)日：2012-07-24
申请号：US11874601
申请日：2007-10-18
申请人： Sachiko Kobayashi , Suigen Kyoh
发明人： Sachiko Kobayashi , Suigen Kyoh
IPC分类号： G06F17/32
CPC分类号： G06F17/5081
摘要： A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include the first modification area by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area.
摘要翻译：公开了一种用于产生半导体集成电路的设计图案的设计布局生成方法。该方法包括：通过第一修改方法修改从设计布局提取的第一修改区域，以及修改从设计布局提取的第二修改区域，以便通过基于模式修改的第二修改方法来包括第一修改区域从第二修改区域中的至少部分设计布局计算出的准则。

28. 发明授权

US08227151B2 Flare correction method, method for manufacturing mask for lithography, and method for manufacturing semiconductor device 有权
标题翻译：光斑修正方法，光刻用掩模的制造方法以及半导体装置的制造方法
公开(公告)号：US08227151B2
公开(公告)日：2012-07-24
申请号：US12868779
申请日：2010-08-26
申请人： Ryoichi Inanami , Suigen Kyoh
发明人： Ryoichi Inanami , Suigen Kyoh
IPC分类号： G03F1/70 , G03F7/20 , G06F17/50
CPC分类号： G03F7/70941 , G03F1/70 , G03F7/70558
摘要： In one embodiment, a flare correction method is disclosed. The method can acquire a flare point spread function. The method can calculate a pattern density distribution in a first region of the mask, the distance from the pattern being equal to or shorter than a predetermined value in the first region. The method can calculate pattern coverage in a second region of the mask, the distance from the pattern being longer than the predetermined value. The method can calculate a first flare distribution with respect to the pattern by performing convolution integration between the flare point spread function corresponding to the first region and the pattern density distribution. The method can calculate a flare value corresponding to the second region by multiplying a value of integral of the flare point spread function corresponding to the second region by the pattern coverage. The method can calculate a second flare distribution by adding the flare value to the first flare distribution. In addition, the method can correct the pattern based on the second flare distribution.
摘要翻译：在一个实施例中，公开了一种闪光校正方法。该方法可以获得耀斑点扩散函数。该方法可以计算掩模的第一区域中的图案密度分布，在图案的距离等于或小于第一区域中的预定值。该方法可以计算掩模的第二区域中的图案覆盖，距离图案的距离长于预定值。该方法可以通过执行与第一区域相对应的闪点扩展函数与图案密度分布之间的卷积积分来计算相对于图案的第一耀斑分布。该方法可以通过将对应于第二区域的闪点扩散函数的积分值乘以图案覆盖来计算与第二区域相对应的耀斑值。该方法可以通过向第一个耀斑分布添加耀斑值来计算第二个耀斑分布。此外，该方法可以基于第二个耀斑分布来校正模式。

29. 发明申请

US20110097827A1 PATTERN FORMATION METHOD AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：图案形成方法和制造半导体器件的方法
公开(公告)号：US20110097827A1
公开(公告)日：2011-04-28
申请号：US12882944
申请日：2010-09-15
申请人： Masayuki HATANO , Suigen Kyoh , Tetsuro Nakasugi
发明人： Masayuki HATANO , Suigen Kyoh , Tetsuro Nakasugi
IPC分类号： H01L21/66 , B29C59/02
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , G03F9/00
摘要： In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern.
摘要翻译：在一个实施例中，公开了图案形成方法。该方法可以将液态树脂材料放置在工件基板上。该方法可以将模板压靠树脂材料并测量模板的突起的下表面与工件基板的上表面之间的距离。模板包括图案形成区域和围绕图案形成区域的周边区域。在图案形成区域中形成用于电路图案形成的图案，并且在周向区域中形成突起。该方法可以通过在压制模板的状态下固化树脂材料来形成树脂图案。此外，该方法可以将模板与树脂图案分离。

30. 发明授权

US07266801B2 Design pattern correction method and mask pattern producing method 有权
标题翻译：设计图案校正方法和掩模图案制作方法
公开(公告)号：US07266801B2
公开(公告)日：2007-09-04
申请号：US11012613
申请日：2004-12-16
申请人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
发明人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
摘要翻译：公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

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