专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080160947A1 Mechanism for controlling amplifier gain in a radio receiver 失效
标题翻译：控制无线电接收机放大器增益的机制
公开(公告)号：US20080160947A1
公开(公告)日：2008-07-03
申请号：US11648413
申请日：2006-12-29
申请人： Chunyu Xin , G. Tyson Tuttle , Scott D. Willingham , Peter J. Vancorenland
发明人： Chunyu Xin , G. Tyson Tuttle , Scott D. Willingham , Peter J. Vancorenland
IPC分类号： H04B1/06
CPC分类号： H03G3/3068
摘要： A radio receiver such as a frequency modulation (FM) receiver, for example, includes a radio frequency (RF) amplifier having an adjustable gain output. The RF amplifier may be configured to receive and amplify an incoming RF signal. The receiver also includes an intermediate frequency (IF) amplifier having an adjustable gain output. The IF amplifier may be configured to receive and amplify an IF signal that corresponds to the RF signal. The receiver also includes a gain control unit that is coupled to the RF amplifier and the IF amplifier. The gain control unit may be configured to independently adjust the gain of each of the RF amplifier and the IF amplifier, dependent upon a peak output level of both the RF amplifier and the IF amplifier.
摘要翻译：诸如调频（FM）接收机的无线电接收机例如包括具有可调增益输出的射频（RF）放大器。 RF放大器可以被配置为接收和放大输入RF信号。接收机还包括具有可调增益输出的中频（IF）放大器。 IF放大器可以被配置为接收和放大对应于RF信号的IF信号。接收机还包括耦合到RF放大器和IF放大器的增益控制单元。增益控制单元可以被配置为根据RF放大器和IF放大器的峰值输出电平独立地调节每个RF放大器和IF放大器的增益。

22. 发明授权

US07362826B2 Receiver including an oscillation circuit for generating an image rejection calibration tone 有权
标题翻译：接收机包括用于产生镜像抑制校准色调的振荡电路
公开(公告)号：US07362826B2
公开(公告)日：2008-04-22
申请号：US10673905
申请日：2003-09-29
申请人： Scott D. Willingham
发明人： Scott D. Willingham
IPC分类号： H03D3/18
CPC分类号： H04B1/30 , H04B17/21
摘要： A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.
摘要翻译：接收器电路包括被配置为产生校准音调和锁相环（PLL）参考信号的振荡器电路。可以将VCO的输出频率除以相应的量，以导出期望的校准音频率和期望的PLL参考信号频率。除了振荡器电路之外，接收器电路还可以包括被配置为产生相对于PLL参考信号锁相的PLL输出信号的锁相电路。在校准模式期间，可以使用正交发生器来产生取决于PLL输出信号的正交混频器本地振荡器信号，并且可以使用同相/正交混频器将校准音调与正交混频器LO信号混合。

23. 发明申请

US20080081583A1 SYSTEM AND METHOD FOR DETERMINING A RESONANT FREQUENCY IN A COMMUNICATIONS DEVICE 有权
标题翻译：用于确定通信设备中的谐振频率的系统和方法
公开(公告)号：US20080081583A1
公开(公告)日：2008-04-03
申请号：US11536900
申请日：2006-09-29
申请人： Ligang Zhang , Scott D. Willingham , Peter J. Vancorenland , Yunteng Huang
发明人： Ligang Zhang , Scott D. Willingham , Peter J. Vancorenland , Yunteng Huang
IPC分类号： H04B1/18
CPC分类号： H03J5/244 , H03J2200/10
摘要： A communications device including communications circuitry, tunable filter circuitry including a node configured to pass a signal between an antenna and the communication circuitry, and control circuitry configured to cause energy in the tunable filter circuitry to be adjusted for a time period and configured to determine a resonant frequency of the tunable filter circuitry from oscillations on the node caused by the energy subsequent to the time period is provided.
摘要翻译：包括通信电路的通信设备，包括被配置为在天线和通信电路之间传递信号的节点的可调谐滤波器电路以及被配置为使得可调滤波器电路中的能量被调整一段时间并被配置为确定提供可调谐滤波器电路的谐振频率与由该时间段之后的能量引起的节点上的振荡。

24. 发明授权

US07230504B1 Controlled oscillator 有权
标题翻译：受控振荡器
公开(公告)号：US07230504B1
公开(公告)日：2007-06-12
申请号：US11216496
申请日：2005-08-31
申请人： Augusto M. Marques , Scott D. Willingham
发明人： Augusto M. Marques , Scott D. Willingham
IPC分类号： H03B5/00
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/124 , H03B5/1265 , H03B2201/0266
摘要： A controlled oscillator circuit includes an amplifier including a first transistor coupled between a first node and a reference node, and a second transistor coupled between a second node and the reference node. The gate of first transistor and the gate of the second transistor may be cross-coupled. The oscillator may also include one or more variable capacitance circuits coupled between the first node and the second node, each including a first capacitor coupled between the first node and a third node, and a second capacitor coupled between the second node and a fourth node. Each variable capacitance circuit may also include a third, a fourth and a fifth transistor interconnected to selectively couple the first and second capacitors to the reference node. The third, fourth and fifth transistors may be low voltage transistors and the first and the second transistors may be high voltage transistors.
摘要翻译：受控振荡器电路包括放大器，其包括耦合在第一节点和参考节点之间的第一晶体管，以及耦合在第二节点和参考节点之间的第二晶体管。第一晶体管的栅极和第二晶体管的栅极可以是交叉耦合的。振荡器还可以包括耦合在第一节点和第二节点之间的一个或多个可变电容电路，每个可变电容电路包括耦合在第一节点和第三节点之间的第一电容器，以及耦合在第二节点和第四节点之间的第二电容器。每个可变电容电路还可以包括互连以将第一和第二电容器选择性地耦合到参考节点的第三，第四和第五晶体管。第三，第四和第五晶体管可以是低电压晶体管，并且第一和第二晶体管可以是高压晶体管。

25. 发明授权

US07064598B2 Radio frequency CMOS buffer circuit and method 失效
标题翻译：射频CMOS缓冲电路及方法
公开(公告)号：US07064598B2
公开(公告)日：2006-06-20
申请号：US10809195
申请日：2004-03-25
申请人： Scott D. Willingham , Augusto M. Marques
发明人： Scott D. Willingham , Augusto M. Marques
IPC分类号： H03L5/00
CPC分类号： H03K19/018571
摘要： A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.
摘要翻译：缓冲器（40）包括具有用于接收输入信号的第一端子的电容器（42）和第二端子; 第一晶体管（44），具有用于接收第一电源电压的第一电流电极，耦合到电容器（42）的第二端子的控制电极和用于提供缓冲器（40）的输出信号的第二电流电极， ; 以及第二晶体管（45），其具有耦合到所述第一晶体管（44）的所述第二电流电极的第一电流电极，耦合到所述电容器（42）的所述第二端子的控制电极和用于接收第二晶体管电源电压。选择电容器（42）的电容以减小输入信号的峰 - 峰电压摆幅，使得在第一（44）和第（45）晶体管的控制电极处的峰 - 峰电压摆幅小于或等于第一和第二电源电压之间的差。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式