会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 22. 发明授权
    • Slew rate control circuit
    • 压摆率控制电路
    • US06075379A
    • 2000-06-13
    • US12120
    • 1998-01-22
    • Nazar S. HaiderSrinivasan RajagopalanCau L. Nguyen
    • Nazar S. HaiderSrinivasan RajagopalanCau L. Nguyen
    • H03K19/003H03K19/0185H03K17/16H03K5/12
    • H03K19/018585H03K19/00384
    • Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.
    • 简而言之,根据本发明的一个实施例,用于处理器的转换速率控制电路包括:产生表示制造的晶体管的速度的信号的电路配置; 以及电路配置,至少部分地基于表示制造的晶体管的速度的信号,调整由用于处理器的输出缓冲器的预驱动器级产生的电流量。 简而言之,根据本发明的另一实施例,集成电路包括:用于缓冲器的转换速率控制电路,包括:能够存储至少一个二进制数字信号的寄存器,预驱动器和至少一个预驱动器 单元耦合到前驱动器。 所述至少一个预驱动器单元耦合到所述预驱动器和寄存器,以便至少部分地基于所述至少一个二进制数字信号来修改由所述预驱动器产生的电流量。
    • 23. 发明授权
    • Timed one-shot active termination device
    • 定时一次性主动终端设备
    • US6072342A
    • 2000-06-06
    • US907933
    • 1997-08-11
    • Nazar S. HaiderSrinivasan Rajagopalan
    • Nazar S. HaiderSrinivasan Rajagopalan
    • G06F13/40H03K19/00H03K19/0185H03K3/00H03K19/094
    • H03K19/0016G06F13/4086H03K19/01855
    • A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state. The second transistor is turned on for a period determined by the clock signal driving the flip flop, the type of flip-flop, and, optionally, additional logic gates, when the signal transitions from the first voltage state to the second voltage state.
    • 当在其输入处检测到处于第一电压状态的信号时,用于驱动GTL型总线的电路主动地驱动总线走向第一参考电压,并且当所选择的周期中的信号被主动地驱动总线轨迹朝向第二参考电压 其输入从第一电压状态转变到第二电压状态。 电路包括用于存储信号的顺序电压状态的触发器,用于将信号的当前电压状态与信号的先前电压状态的复制品以及互补导电类型的第一和第二晶体管进行比较的逻辑,用于 激活时分别将总线走线驱动到第一或第二参考电压。 当信号处于第一电压状态时,第一晶体管导通。 当信号从第一电压状态转变到第二电压状态时,第二晶体管导通由驱动触发器的时钟信号,触发器类型和可选地附加的逻辑门确定的时间段。