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21. 发明申请

US20070048943A1 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array 有权
标题翻译：用于高密度，低电压逻辑和存储器阵列的垂直环绕栅极场效应晶体管
公开(公告)号：US20070048943A1
公开(公告)日：2007-03-01
申请号：US11438419
申请日：2006-05-23
申请人： Sanh Tang , Robert Burke , Anand Srinivasan
发明人： Sanh Tang , Robert Burke , Anand Srinivasan
IPC分类号： H01L21/336
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
摘要翻译：具有环绕栅极的垂直晶体管和制造这种晶体管的方法。环绕栅极（WAG）垂直晶体管通过其中晶体管的源极，漏极和沟道区域通过制造工艺自动限定和对准而不进行光刻图案化的工艺制造。

22. 发明申请

US20070048942A1 Methods of forming field effect transistors on substrates 失效
标题翻译：在衬底上形成场效应晶体管的方法
公开(公告)号：US20070048942A1
公开(公告)日：2007-03-01
申请号：US11215477
申请日：2005-08-30
申请人： Robert Hanson , Sanh Tang
发明人： Robert Hanson , Sanh Tang
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8234
CPC分类号： H01L29/66666 , H01L21/26513 , H01L21/823418 , H01L21/823437 , H01L21/823487 , H01L29/6659 , H01L29/66621 , H01L29/7834
摘要： The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成场效应晶体管的方法。在一个实施方案中，本发明包括在衬底上形成场效应晶体管的方法，其中场效应晶体管包括一对导电掺杂的源极/漏极区域，在该对源极/漏极区域之间接收的沟道区域，以及晶体管栅极可靠地接收在沟道区域。这种实现包括在沉积材料之前对该对源极/漏极区进行掺杂剂激活退火，从而制造晶体管栅极的导电部分。考虑了其他方面和实现。

23. 发明申请

US20060267472A1 Field emission tips, arrays, and devices 审中-公开
标题翻译：场发射提示，阵列和设备
公开(公告)号：US20060267472A1
公开(公告)日：2006-11-30
申请号：US11500124
申请日：2006-08-07
申请人： Guy Blalock , Sanh Tang , Zhaohui Huang
发明人： Guy Blalock , Sanh Tang , Zhaohui Huang
IPC分类号： H01J1/16 , H01J1/02 , H01J1/00
CPC分类号： H01J1/304 , H01J1/3044 , H01J31/127 , H01J2201/30446
摘要： A field emission tip includes a base with a central portion and a tapered portion. The central portion of the base includes a peripheral surface, at least a portion of which is oriented substantially vertically or perpendicularly relative to a plane in which a substrate from which the field emission tip protrudes resides. An apex may be located at an exposed end of the central portion of the base. The tapered portion of the base includes an inclined surface that extends toward the exposed end of the central portion of the base. The tapered portion of the base may be formed from material that is redeposited as the emission tip is fabricated. The apex may be formed, at least in part, from a low work function material, such as one or more of aluminum titanium silicide, titanium silicide nitride, titanium nitride, tri-chromium mono-silicon, and tantalum nitride. Field emission arrays and field emission displays that include such field emission tips are also disclosed.
摘要翻译：场发射尖端包括具有中心部分和锥形部分的基部。基部的中心部分包括外周表面，其外周表面的至少一部分相对于其中场致发射尖端突出的基底所在的平面基本垂直或垂直取向。顶点可以位于基部的中心部分的暴露端。基部的锥形部分包括朝向基部的中心部分的暴露端延伸的倾斜表面。基底的锥形部分可以由制造发射尖端时再沉积的材料形成。顶点可以至少部分地由低功函数材料形成，例如铝硅化钛，硅化钛氮化物，氮化钛，三铬单硅和氮化钽中的一种或多种。还公开了包括这种场发射尖端的场致发射阵列和场致发射显示器。

24. 发明申请

US20060258107A1 Methods of forming field effect transistors and methods of forming field effect transistor gates and gate lines 审中-公开
标题翻译：形成场效应晶体管的方法和形成场效应晶体管栅极和栅极线的方法
公开(公告)号：US20060258107A1
公开(公告)日：2006-11-16
申请号：US11489381
申请日：2006-07-19
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

25. 发明申请

US20060151880A1 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads 有权
公开(公告)号：US20060151880A1
公开(公告)日：2006-07-13
申请号：US11032975
申请日：2005-01-10
申请人： Sanh Tang , Mark Tuttle , Keith Cook
发明人： Sanh Tang , Mark Tuttle , Keith Cook
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05181 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05571 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/04941 , H01L2224/05552
摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

26. 发明申请

US20060043450A1 Vertical transistors 有权
公开(公告)号：US20060043450A1
公开(公告)日：2006-03-02
申请号：US10934621
申请日：2004-09-02
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L29/94
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10814 , H01L27/10876 , H01L27/10888 , H01L29/66666
摘要： Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.

27. 发明申请

US20060043429A1 Contact structure and contact liner process 有权
公开(公告)号：US20060043429A1
公开(公告)日：2006-03-02
申请号：US10925527
申请日：2004-08-24
申请人： Grant Huglin , Robert Burke , Sanh Tang
发明人： Grant Huglin , Robert Burke , Sanh Tang
IPC分类号： H01L29/745 , H01L29/76 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76852 , H01L21/76885 , H01L27/10888
摘要： A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.

28. 发明授权

US06437369B1 Method of forming dynamic random access memory circuitry and dynamic random access memory 失效
标题翻译：形成动态随机存取存储器电路和动态随机存取存储器的方法
公开(公告)号：US06437369B1
公开(公告)日：2002-08-20
申请号：US09089751
申请日：1998-06-02
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/1203 , H01L28/40
摘要： A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; l) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions. Also contemplated is a DRAM array having sources and drains formed within an SOI layer, wherein capacitors of the array comprise trenches formed within a monocrystalline substrate, with the substrate comprising a common cell plate of the capacitors.
摘要翻译：形成动态随机存取存储器电路的半导体处理方法包括：a）提供导电电容器单元板基板; b）在电池板上提供电绝缘层; c）在绝缘层上提供半导体材料层，从而限定绝缘体上半导体（SOI）层; d）图案化和蚀刻SOI层以限定岛之间的有源区域岛和隔离沟槽; e）用绝缘材料填充隔离沟; f）提供通过SOI层和绝缘层的电容器开口进入电池板衬底; g）在电容器开口内的电池板衬底上提供电容器电介质层; h）在电容器开口内的电介质层上提供相应的电容器存储节点，各个存储节点与SOI层欧姆连接; i）在提供存储节点之后，用绝缘材料填充电容器容器开口的剩余部分; j）在SOI层岛顶上提供栅介质层; k）在岛上的栅极电介质层和填充的隔离沟槽之上提供导电字线; l）在SOI层内提供相对的FET源极和漏极区域; 并且m）在字线外部提供位线，位线与选择的漏极区域连接。还考虑了具有形成在SOI层内的源极和漏极的DRAM阵列，其中阵列的电容器包括形成在单晶衬底内的沟槽，衬底包括电容器的公共电池板。

29. 发明授权

US5838068A Integrated circuitry with interconnection pillar 失效
标题翻译：具有互连柱的集成电路
公开(公告)号：US5838068A
公开(公告)日：1998-11-17
申请号：US903198
申请日：1997-07-15
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L21/822 , H01L23/485 , H01L27/04 , H01L29/417 , H01L23/48 , H01L23/52 , H01L23/62 , H01L29/40
CPC分类号： H01L29/417 , H01L21/76885 , H01L23/485 , H01L2924/0002 , Y10S257/903 , Y10S438/97
摘要： A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching. Integrated circuitry is also disclosed.
摘要翻译：半导体处理方法包括：a）提供具有要与其进行电连接的基极区域的基板; b）提供第一层导电第一材料; c）在第一层上提供蚀刻停止层; d）通过蚀刻停止层和第一层蚀刻到基底区域的接触开口; e）在所述蚀刻停止层的外部和所述接触开口内提供第二层第一材料，其厚度大于所述第一层厚度并向外延伸超出所述接触开口上边缘; f）去除第二层的第一材料并在接触件内限定第二层塞，第二层塞具有向外延伸超过接触开口上边缘的最外表面，从而使第二层塞具有比第一层层; g）从第一层和第二层插塞向外掩蔽，以限定掩模图案，用于定义来自第一层的电路部件，该第一层通过第二层插塞与基部区域连接; 以及h）蚀刻所述第一层和第二层插塞的未屏蔽部分以限定通过所述第二层插塞与所述基底区域连接的电路部件，所述第二层插塞的厚度与所述第一层限制蚀刻的厚度相比较大在蚀刻期间进入基底区域。还公开了集成电路。

30. 发明授权

US5834805A Dynamic random access memory circuit array and memory cell 失效
标题翻译：动态随机存取存储器电路阵列和存储单元
公开(公告)号：US5834805A
公开(公告)日：1998-11-10
申请号：US717015
申请日：1996-09-20
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/76
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/1203 , H01L28/40
摘要： A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; 1) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions. Also contemplated is a DRAM array having sources and drains formed within an SOI layer, wherein capacitors of the array comprise trenches formed within a monocrystalline substrate, with the substrate comprising a common cell plate of the capacitors.
摘要翻译：形成动态随机存取存储器电路的半导体处理方法包括：a）提供导电电容器单元板基板; b）在电池板上提供电绝缘层; c）在绝缘层上提供半导体材料层，从而限定绝缘体上半导体（SOI）层; d）图案化和蚀刻SOI层以限定岛之间的有源区域岛和隔离沟槽; e）用绝缘材料填充隔离沟; f）提供通过SOI层和绝缘层的电容器开口进入电池板衬底; g）在电容器开口内的电池板衬底上提供电容器电介质层; h）在电容器开口内的电介质层上提供相应的电容器存储节点，各个存储节点与SOI层欧姆连接; i）在提供存储节点之后，用绝缘材料填充电容器容器开口的剩余部分; j）在SOI层岛顶上提供栅介质层; k）在岛上的栅极电介质层和填充的隔离沟槽之上提供导电字线; 1）在SOI层内提供相对的FET源极和漏极区域; 并且m）在字线外部提供位线，位线与选择的漏极区域连接。还考虑了具有形成在SOI层内的源极和漏极的DRAM阵列，其中阵列的电容器包括形成在单晶衬底内的沟槽，衬底包括电容器的公共电池板。

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