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21. 发明申请

US20060053190A1 Construction of a folded leading zero anticipator 审中-公开
标题翻译：构建一个折叠的领先的零预期者
公开(公告)号：US20060053190A1
公开(公告)日：2006-03-09
申请号：US10937693
申请日：2004-09-09
申请人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller , Yonetaro Totsuka
发明人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller , Yonetaro Totsuka
IPC分类号： G06F7/38
CPC分类号： G06F5/012 , G06F7/74
摘要： An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA that compute edge vectors for the most and least significant bits of intermediate resultant vectors. Therefore, a LZA can be easily folded to reduce the area requirement so as to increase the versatility of the LZA.
摘要翻译：提供了一种装置，方法和计算机程序，用于预测浮点（FP）计算的前导零。传统领先的零预期（LZA）通常非常广泛。为了减小LZA的宽度，它被细分为两个较小的LZA，它们计算中间合成向量的最高有效位和最低有效位的边缘向量。因此，LZA可以容易地折叠以减小面积要求，从而增加LZA的通用性。

22. 发明授权

US06914453B2 Integrated logic and latch design with clock gating at static input signals 失效
标题翻译：具有静态输入信号时钟门控的集成逻辑和锁存器设计
公开(公告)号：US06914453B2
公开(公告)日：2005-07-05
申请号：US10616850
申请日：2003-07-10
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.
摘要翻译：提供了一种用于实现具有集成逻辑和锁存器设计的逻辑电路的方法和装置。时钟输入提供给逻辑电路。一个或多个静态信号输入进一步提供给逻辑电路。通过用时钟信号动态选通一个或多个静态信号输入来产生一个或多个动态信号输入。一个或多个动态信号输入被施加到逻辑电路，并且产生逻辑电路的一个或多个动态信号输出。一个或多个动态信号输出被预充电，并且评估一个或多个动态信号输出。当一个或多个动态信号输出既不被预充电也不被评估时，一个或多个动态信号输出被保持。一个或多个动态信号输出被转换成一个或多个静态信号输出。

23. 发明申请

US20080195684A1 Apparatus for Reducing the Latency of Sum-Addressed Shifters 失效
标题翻译：减少并排移位器延迟的装置
公开(公告)号：US20080195684A1
公开(公告)日：2008-08-14
申请号：US12105726
申请日：2008-04-18
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

24. 发明授权

US07290023B2 High performance implementation of exponent adjustment in a floating point design 失效
标题翻译：浮点设计中指数调整的高性能实现
公开(公告)号：US07290023B2
公开(公告)日：2007-10-30
申请号：US10718303
申请日：2003-11-20
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin D. Tran
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin D. Tran
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/74
摘要： A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
摘要翻译：一个浮点单元（FPU），产生一个校正信号和一个反向的前导零信号。指数逻辑被配置为生成指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑，配置为接收指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑还被配置为将反向引导零信号加到第一递增指数值和第二递增指数值，从而产生指数输出值，第一递增指数输出值和第二递增指数输出值。然后选择指数输出值，第一递增指数输出值或第二指数输出值。

25. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

26. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

27. 发明授权

US07710796B2 Level shifter for boosting wordline voltage and memory cell performance 有权
标题翻译：电平移位器用于提高字线电压和存储单元性能
公开(公告)号：US07710796B2
公开(公告)日：2010-05-04
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

28. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

29. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

30. 发明授权

US07170328B2 Scannable latch 失效
标题翻译：可扫描闩锁
公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

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