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21. 发明专利

DE102004025925A1 Formation of self-aligned contact structure involves planarizing upper conductive layer and sacrificial mask patterns until upper surfaces of recessed mask patterns are exposed to form plug surrounded by spacer 未知
公开(公告)号：DE102004025925A1
公开(公告)日：2005-02-03
申请号：DE102004025925
申请日：2004-05-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN CHEOL-JU , CHUNG TAE-YOUNG
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/283
摘要： A self-aligned contact structure is formed by forming a spacer that covers a sidewall of a self-aligned contact hole; forming an upper conductive layer that fills the self-aligned contact hole on the entire surface of a semiconductor substrate having the spacer; and planarizing the upper conductive layer and sacrificial mask patterns until upper surfaces of recessed mask patterns are exposed to form a plug surrounded by the spacer. Formation of a self-aligned contact structure includes forming parallel interconnection patterns (350) on a semiconductor substrate (100), where each interconnection pattern has an interconnection and a mask pattern stacked in sequence; forming interlayer insulating layer patterns that fill gap regions between the interconnection patterns; partially etching the mask patterns to form recessed mask patterns that define grooves between the interlayer insulating layer patterns; forming sacrificial mask patterns (600) that fill the grooves; etching a predetermined region of one of the interlayer insulating layer patterns using the sacrificial mask patterns as etching masks to form a self-aligned contact hole (750) that exposes a predetermined region of the substrate; forming a spacer (650) that covers a sidewall of the self-aligned contact hole; forming an upper conductive layer that fills the self-aligned contact hole on the entire surface of the substrate having the spacer; and planarizing the upper conductive layer and the sacrificial mask patterns until upper surfaces of the recessed mask patterns are exposed to form a plug surrounded by the spacer.

22. 发明专利

GB2400236A Memory capacitors 未知
公开(公告)号：GB2400236A
公开(公告)日：2004-10-06
申请号：GB0324534
申请日：2003-10-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG TAE-YOUNG , LEE JAE-GOO , PARK JE-MIN
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： A two layer storage electrode comprising an upper cup shaped portion 70 and a lower cylindrical or box-shaped portion 40 formed in sacrificial layers 20 and 20. A contact pad 104 is formed in an interlayer insulator 102 and provides electrical contact to the storage electrode. The occurrence of non-open contacts and leaning storage electrodes is reduced.

23. 发明专利

GB2293691B Semiconductor memory devices 未知
公开(公告)号：GB2293691B
公开(公告)日：1996-06-19
申请号：GB9521898
申请日：1992-09-07
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHIN DAE-JE , CHUNG TAE-YOUNG , PARK YOUNG-WOO
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/92

24. 发明专利

ITMI922067D0 未知
公开(公告)号：ITMI922067D0
公开(公告)日：1992-09-04
申请号：ITMI922067
申请日：1992-09-04
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHIN DAE-JE , CHUNG TAE-YOUNG , PARK YOUNG-WOO
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108

25. 发明专利

DE102004021636B4 未知
公开(公告)号：DE102004021636B4
公开(公告)日：2010-02-04
申请号：DE102004021636
申请日：2004-05-03
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN CHEOL-JU , CHO CHANG-HYUN , CHUNG TAE-YOUNG
IPC分类号： H01L21/28 , H01L27/108 , H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/088 , H01L29/417
摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

26. 发明专利

DE102004025925B4 未知
公开(公告)号：DE102004025925B4
公开(公告)日：2007-02-08
申请号：DE102004025925
申请日：2004-05-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN CHEOL-JU , CHUNG TAE-YOUNG
IPC分类号： H01L21/28 , H01L21/283 , H01L21/60 , H01L21/768
摘要： A self-aligned contact structure is formed by forming a spacer that covers a sidewall of a self-aligned contact hole; forming an upper conductive layer that fills the self-aligned contact hole on the entire surface of a semiconductor substrate having the spacer; and planarizing the upper conductive layer and sacrificial mask patterns until upper surfaces of recessed mask patterns are exposed to form a plug surrounded by the spacer. Formation of a self-aligned contact structure includes forming parallel interconnection patterns (350) on a semiconductor substrate (100), where each interconnection pattern has an interconnection and a mask pattern stacked in sequence; forming interlayer insulating layer patterns that fill gap regions between the interconnection patterns; partially etching the mask patterns to form recessed mask patterns that define grooves between the interlayer insulating layer patterns; forming sacrificial mask patterns (600) that fill the grooves; etching a predetermined region of one of the interlayer insulating layer patterns using the sacrificial mask patterns as etching masks to form a self-aligned contact hole (750) that exposes a predetermined region of the substrate; forming a spacer (650) that covers a sidewall of the self-aligned contact hole; forming an upper conductive layer that fills the self-aligned contact hole on the entire surface of the substrate having the spacer; and planarizing the upper conductive layer and the sacrificial mask patterns until upper surfaces of the recessed mask patterns are exposed to form a plug surrounded by the spacer.

27. 发明专利

GB2400236B Semiconductor device having a capacitor and method of fabricating same 未知
公开(公告)号：GB2400236B
公开(公告)日：2005-09-14
申请号：GB0324534
申请日：2003-10-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG TAE-YOUNG , LEE JAE-GOO , PARK JE-MIN
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： A two layer storage electrode comprising an upper cup shaped portion 70 and a lower cylindrical or box-shaped portion 40 formed in sacrificial layers 20 and 20. A contact pad 104 is formed in an interlayer insulator 102 and provides electrical contact to the storage electrode. The occurrence of non-open contacts and leaning storage electrodes is reduced.

28. 发明专利

DE10347458A1 Semiconductor device forming method e.g. for embedded memory, involves forming single layer spacer on side walls of conductive pattern by etching one spacer layer using another spacer as mask 未知
公开(公告)号：DE10347458A1
公开(公告)日：2004-10-21
申请号：DE10347458
申请日：2003-10-13
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE DONG-JUN , CHUNG TAE-YOUNG , LEE JAE-GOO
IPC分类号： H01L21/28 , H01L21/00 , H01L21/60 , H01L21/762 , H01L21/768 , H01L21/8239 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： A spacer layer (70) formed between the adjacent conductive patterns (55) comprising bit line (50) and capping layer (60) is etched through interlayer insulation film (20) and another spacer layer (80) is used as mask to form single layer spacer on side walls of conductive patterns. Independent claims are also included for the following: (1) semiconductor memory formation method; (2) semiconductor device; and (3) semiconductor memory.

29. 发明专利

DE19930295A1 Columnar capacitor storage node useful in a DRAM 未知
公开(公告)号：DE19930295A1
公开(公告)日：2000-01-13
申请号：DE19930295
申请日：1999-07-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KWAK DONG-HWA , HWANG YOO-SANG , CHUNG TAE-YOUNG
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
摘要： A capacitor storage node, comprising a thick easily etched conductive layer (110) and a thin protective conductive layer (114), is new. A capacitor storage node is formed by: (a) forming a contact plug (107) in an insulation layer (104) on a semiconductor substrate (100); (b) successively forming a first metal barrier layer (108), a first conductive layer (110) and a second metal barrier layer (112) on the insulation layer and on the plug; (c) applying a second thinner conductive layer (114); (d) etching the layers using a mask to form a multilayer columnar storage node electrically connected to the plug; (e) forming a metal spacer barrier layer (118a) on both side walls of the node; and (f) forming a conductive spacer layer (120a) on both side walls of the metal spacer barrier layer. Independent claims are also included for the following: (i) a similar process in which the metal barrier layers and the metal spacer barrier layer are omitted; and (ii) capacitor storage nodes produced by the above processes. Preferred Features: The metal barrier layers and the metal spacer barrier layer, or the first conductive layer used in process (i), consist of TiN, TiAlN, TiSiN, TaAlN, ruthenium oxide, iridium oxide, lanthanum-strontium-cobalt oxide or a conductive oxide of Ba, Sr and Ru.

30. 发明专利

GB2290908A Semiconductor memory device capacitors 未知
公开(公告)号：GB2290908A
公开(公告)日：1996-01-10
申请号：GB9514098
申请日：1992-09-07
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHIN DAE-JE , CHUNG TAE-YOUNG , PARK YOUNG-WOO
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/92
摘要： A storage capacitor has a storage electrode 36 and a dielectric layer 40 formed on the storage electrode, wherein the storage electrode 36 is of polysilicon and includes a plurality of microtrenches and/or microcylinders formed on its surface. Further, the storage electrode 36 with the plurality of microtrenches and/or microcylinders is formed by forming hemispherical grains on a surface of the storage electrode, forming an etching mask layer on side walls of the respective grains, and performing an anisotropic etching by using the etching mask layer as a mask.

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