专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20100191920A1 Providing Address Range Coherency Capability To A Device 失效
标题翻译：为设备提供地址范围一致性能力
公开(公告)号：US20100191920A1
公开(公告)日：2010-07-29
申请号：US12360533
申请日：2009-01-27
申请人： Zhen Fang , David J. Harriman , Michael W. Leddige
发明人： Zhen Fang , David J. Harriman , Michael W. Leddige
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/0835 , G06F12/0888 , G06F12/1027
摘要： In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到输入/输出（IO）互连的设备接收存储器请求的方法，访问与IO互连关联的映射表，以确定包括存储器的地址的地址范围请求是一致的，如果是，则发送存储器请求和一致性指示符以指示地址处的数据的相干状态，否则发送存储器请求和一致性指示符以指示非相干状态。描述和要求保护其他实施例。

22. 发明申请

US20070238322A1 Technique for blind-mating daughtercard to mainboard 有权
标题翻译：盲卡子卡到主板的技术
公开(公告)号：US20070238322A1
公开(公告)日：2007-10-11
申请号：US11393540
申请日：2006-03-30
申请人： Pascal C. Meier , Michael W. Leddige , Mohiuddin Mazumder , Mark Trobough , Alok Tripathi , Ven R. Holalkere
发明人： Pascal C. Meier , Michael W. Leddige , Mohiuddin Mazumder , Mark Trobough , Alok Tripathi , Ven R. Holalkere
IPC分类号： H01R12/00
CPC分类号： H01R12/52 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/10189 , H05K2201/10325 , H05K2201/10719
摘要： An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable (“flex cable”) secured to the PCB. The apparatus also includes a daughtercard having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector which provides an electrically conductive connection between the first flex cable and the second flex cable. The connector is positioned to sandwich a portion of the first flex cable between the connector and the PCB.
摘要翻译：一种装置包括固定到PCB的印刷电路板（PCB）和第一柔性导电电缆（“柔性电缆”）。该装置还包括具有邻近PCB的端部的子卡和固定到子卡的第二柔性电缆。该装置还包括连接器，其在第一柔性电缆和第二柔性电缆之间提供导电连接。连接器被定位成将第一柔性电缆的一部分夹在连接器和PCB之间。

23. 发明授权

US06918078B2 Systems with modules sharing terminations 失效
标题翻译：具有模块共享终端的系统
公开(公告)号：US06918078B2
公开(公告)日：2005-07-12
申请号：US09911634
申请日：2001-07-23
申请人： James A. McCall , Michael W. Leddige
发明人： James A. McCall , Michael W. Leddige
IPC分类号： G11C5/06 , H05K1/02 , H05K1/11 , H05K1/14 , H03M13/00
CPC分类号： H05K1/0246 , G11C5/063 , H05K1/117 , H05K1/141 , H05K2201/044 , H05K2201/09254 , H05K2201/10022
摘要： In some embodiments, the invention includes a system having first, second, third and fourth modules; and a circuit board including first, second, third, and fourth module connectors to receive the first and second modules, respectively. The system includes among other things a first group of paths of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, back to the second module connector, to terminations, wherein the first group of paths include a first short loop through section in the first module and a second short loop through section in the second module, to each couple to stubs for corresponding first and second chips of the first and second modules.
摘要翻译：在一些实施例中，本发明包括具有第一，第二，第三和第四模块的系统; 以及电路板，包括分别接收第一和第二模块的第一，第二，第三和第四模块连接器。该系统包括第一组导体，从电路板延伸到第一模块连接器，第一组件，第一模块连接器，电路板，第二模块连接器，第二模块连接器模块，返回到第二模块连接器，到终端，其中第一组路径包括第一模块中的第一短循环部分和第二模块中的第二短循环部分，每个耦合到短截线用于对应的第一和第一和第二模块的第二芯片。

24. 发明授权

US06587912B2 Method and apparatus for implementing multiple memory buses on a memory module 有权
标题翻译：用于在存储器模块上实现多个存储器总线的方法和装置
公开(公告)号：US06587912B2
公开(公告)日：2003-07-01
申请号：US09163860
申请日：1998-09-30
申请人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
发明人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
IPC分类号： G06F1200
CPC分类号： G06F13/4256
摘要： A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
摘要翻译：计算机系统存储器模块包括双向中继器集线器，其在第一方向上将第一端口中的存储器总线信号作为输入，再生存储器信号，并将第二端口处的再生存储器信号作为至少一个单独的信号，用于耦合到存储器总线，用于每个再生的分离信号。在第二方向上，双向中继器集线器将第二端口处的至少一个存储器总线信号作为输入，再生每个输入存储器总线信号，并在第一端口处输出再生的存储器信号以耦合到存储器总线。

25. 发明授权

US06515555B2 Memory module with parallel stub traces 失效
公开(公告)号：US06515555B2
公开(公告)日：2003-02-04
申请号：US09746241
申请日：2000-12-22
申请人： Michael W. Leddige , James A. McCall
发明人： Michael W. Leddige , James A. McCall
IPC分类号： H01P308
CPC分类号： G11C5/06 , G11C5/04 , H05K1/025 , H05K2201/09727 , H05K2201/10689
摘要： A printed circuit board is described. That printed circuit board includes a capacitive load that is coupled to a signal trace. The signal trace has a first section and a second section. The first section is positioned between the capacitive load and the second section. The second section has a first width, and the first section includes first and second lines that each have a width that is smaller than the first width.

26. 发明授权

US06353539B1 Method and apparatus for matched length routing of back-to-back package placement 失效
标题翻译：背对背封装放置匹配长度布线的方法和装置
公开(公告)号：US06353539B1
公开(公告)日：2002-03-05
申请号：US09120517
申请日：1998-07-21
申请人： Bryce D. Horine , Michael W. Leddige
发明人： Bryce D. Horine , Michael W. Leddige
IPC分类号： H05K702
CPC分类号： H05K1/0248 , H05K1/025 , H05K1/181 , H05K2201/09263 , H05K2201/09781 , H05K2201/10159 , H05K2201/10545
摘要： A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad coupled to a first contact on the first component with a second landpad coupled to a corresponding first contact on the second component. A second signal line connects a third landpad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line.
摘要翻译：印刷电路板包括安装在印刷电路板的第一侧上的第一部件。第二个组件具有与第一个组件相同的引脚输出。第二部件安装在印刷电路板的第二侧上。第一信号线将耦合到第一部件上的第一触点的第一焊盘与连接到第二部件上的对应的第一触点的第二焊垫相连。第二信号线将耦合到第一部件上的第二接触件的第三接地板与耦合到第二部件上的对应的第二接点的第四接地焊盘连接。第一信号线的长度与第二信号线的长度相等。

27. 发明申请

US20140181348A1 CROSSTALK AWARE DECODING FOR A DATA BUS 有权
标题翻译：数据总线的CROSSTALK AWARE解码
公开(公告)号：US20140181348A1
公开(公告)日：2014-06-26
申请号：US13844671
申请日：2013-03-15
申请人： Olufemi B. Oluwafemi , Stephen H. Hall , Jason A. Mix , Earl J. Wight , Chaitanya Sreerama , Michael W. Leddige , Paul G. Huray
发明人： Olufemi B. Oluwafemi , Stephen H. Hall , Jason A. Mix , Earl J. Wight , Chaitanya Sreerama , Michael W. Leddige , Paul G. Huray
IPC分类号： G06F13/40
CPC分类号： G06F13/4004 , G06F13/4022
摘要： Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.
摘要翻译：本文描述了用于解码编码数据的技术。根据本技术的设备的示例包括耦合到多个信号线的接收信令模块。信令模块包括接收器，用于在总线的多个信号线上接收多个编码线路电压或电流，其中多个编码线路电压中的每一个对应于数据的加权和。信号模块包括一个比较器，用于以单位间隔确定每条线路的电压电平，并将电压电平转换成数字值。信令模块包括将数字值与数字比特流相关联的查找表。

28. 发明授权

US08631208B2 Providing address range coherency capability to a device 失效
标题翻译：为设备提供地址范围一致性功能
公开(公告)号：US08631208B2
公开(公告)日：2014-01-14
申请号：US12360533
申请日：2009-01-27
申请人： Zhen Fang , David J. Harriman , Michael W. Leddige
发明人： Zhen Fang , David J. Harriman , Michael W. Leddige
IPC分类号： G06F13/00
CPC分类号： G06F12/0835 , G06F12/0888 , G06F12/1027
摘要： In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到输入/输出（IO）互连的设备接收存储器请求的方法，访问与IO互连关联的映射表，以确定包括存储器的地址的地址范围请求是一致的，如果是，则发送存储器请求和一致性指示符以指示地址处的数据的相干状态，否则发送存储器请求和一致性指示符以指示非相干状态。描述和要求保护其他实施例。

29. 发明授权

US07133962B2 Circulator chain memory command and address bus topology 有权
标题翻译：循环链存储器命令和地址总线拓扑
公开(公告)号：US07133962B2
公开(公告)日：2006-11-07
申请号：US10658883
申请日：2003-09-09
申请人： Michael W. Leddige , James A. McCall
发明人： Michael W. Leddige , James A. McCall
IPC分类号： G06F12/00
CPC分类号： G11C8/12 , G11C5/063 , G11C7/1066
摘要： Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.
摘要翻译：本发明的实施例提供了一种存储器命令和地址（CA）总线架构，其可以适应具有降低的信号劣化的较高CA数据输出频率。对于本发明的一个实施例，CA信号被路由到两DIMM /通道存储器总线设计的两个双列直插存储器模块（DIMM）中的第一个。然后将CA信号分成组件，每个CA信号分量通过一组第一DIMM上的动态随机存取存储器（DRAM）芯片串行路由。然后将CA信号组件重新组合并路由到第二个DIMM。然后将重新组合的CA信号再划分成组件，每个CA信号分量被顺序地路由在第一DIMM上的一组动态随机存取存储器（DRAM）芯片，然后CA信号分量被重新组合。在一个实施例中，在路由每个DRAM之后，CA信号在DIMM上终止。

30. 发明授权

US06891899B2 System and method for bit encoding to increase data transfer rate 失效
标题翻译：用于比特编码的系统和方法来提高数据传输速率
公开(公告)号：US06891899B2
公开(公告)日：2005-05-10
申请号：US09810576
申请日：2001-03-19
申请人： Stephen H. Hall , Michael W. Leddige
发明人： Stephen H. Hall , Michael W. Leddige
IPC分类号： H04L25/49 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H04L25/4923
摘要： A system and method for increasing data transfer rate is disclosed. A digital signal waveform that contains one bit of information for every bit time of the digital signal waveform is received. Every three bits of the digital signal waveform is buffered and encoded. The encoding produces an encoded waveform that contains three bits of information for each bit time of the digital signal waveform, therefore, increasing the data transfer rate of the digital signal waveform.
摘要翻译：公开了一种提高数据传输速率的系统和方法。接收包含数字信号波形的每个位时间的一位信息的数字信号波形。数字信号波形的每三位都被缓冲和编码。编码产生编码波形，其中包含数字信号波形的每个位时间的三位信息，因此增加数字信号波形的数据传输速率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式