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21. 发明申请

US20120230700A1 Optical Module Design in an SFP Form Factor to Support Increased Rates of Data Transmission 有权
标题翻译： SFP格式的光模块设计，以支持数据传输速率的提高
公开(公告)号：US20120230700A1
公开(公告)日：2012-09-13
申请号：US13045972
申请日：2011-03-11
申请人： Luca Cafiero , Zhiping Yang , Victor Odisho , Francisco Matus
发明人： Luca Cafiero , Zhiping Yang , Victor Odisho , Francisco Matus
IPC分类号： H04B10/00
CPC分类号： G02B6/4201 , H05K1/117 , H05K2201/09409 , H05K2201/10121
摘要： A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.
摘要翻译：小尺寸可插拔（SFP）模块包括具有插入连接器装置的端部的板。第一组信号焊盘沿端部的SFP板的第一表面的边缘和沿端部的SFP板的第二表面的边缘的第二组信号焊盘排列。第三组信号垫设置在端部处的第二表面上，偏离第二表面的边缘。耦合到第一，第二和第三组信号焊盘的信号焊盘的收发器被配置成经由第三组信号焊盘发送和接收信号，并且经由第一和第二信号焊盘中的至少一个来发送和接收信号套信号垫。

22. 发明授权

US08160094B2 Fibre channel over ethernet 有权
标题翻译：以太网上的光纤通道
公开(公告)号：US08160094B2
公开(公告)日：2012-04-17
申请号：US12485337
申请日：2009-06-16
申请人： Luca Cafiero , Silvano Gai
发明人： Luca Cafiero , Silvano Gai
IPC分类号： H04J3/26
CPC分类号： H04L47/522 , H04L12/4625 , H04L61/106 , H04L61/6022 , H04L61/6045
摘要： The present invention provides methods and devices for implementing a Low Latency Ethernet (“LLE”) solution, also referred to herein as a Data Center Ethernet (“DCE”) solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes (“VLs”) in a single physical connection of a data center or similar network. Some VLs are “drop” VLs, with Ethernet-like behavior, and others are “no-drop” lanes with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs.
摘要翻译：本发明提供了用于实现低延迟以太网（“LLE”）解决方案的方法和设备，这也被称为数据中心以太网（“DCE”）解决方案，其简化了数据中心的连接性并提供了高带宽，低用于承载以太网和存储流量的延迟网络。本发明的一些方面涉及将FC帧变换成适于在以太网上传输的格式。本发明的一些优选实现在数据中心或类似网络的单个物理连接中实现多个虚拟通道（“VL”）。一些VL是“下降”VL，具有类似以太网的行为，而其他VL是类似FC的行为的“不丢弃”通道。本发明的一些优选实施方案提供了基于信用和VL的保证带宽。使用小帧缓冲区时，主动缓冲区管理可实现高可靠性和低延迟。优选地，用于主动缓冲器管理的规则对于丢弃和不丢弃VL是不同的。

23. 发明申请

US20090177849A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

24. 发明授权

US5796732A Architecture for an expandable transaction-based switching bus 失效
标题翻译：基于可扩展事务的交换总线架构
公开(公告)号：US5796732A
公开(公告)日：1998-08-18
申请号：US621720
申请日：1996-03-28
申请人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
发明人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
IPC分类号： H04L12/56 , H04L12/403
CPC分类号： H04L49/102 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/351
摘要： A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.
摘要翻译：交换总线架构能够在具有通过高性能交换总线互连的多个端口的网络交换机内进行有效的数据传输。该架构优选地被实现为新颖的端口接口和转发引擎电路，其协作以根据确保对总线的足够端口访问的2级仲裁策略来有效地向交换总线传输数据和从交换总线接收数据。作为这种协作安排的结果，该架构通过提供足够的总线访问来提供交换机的传输效率，从而在整个交换机中传送准确的数据。

25. 发明授权

US5280500A Method and apparatus for multilevel encoding for a local area network 失效
标题翻译：用于局域网多级编码的方法和装置
公开(公告)号：US5280500A
公开(公告)日：1994-01-18
申请号：US775641
申请日：1991-10-10
申请人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
发明人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
IPC分类号： H03M5/18 , H03M5/20 , H04L25/49
CPC分类号： H04L25/4917 , H03M5/18 , H03M5/20
摘要： A multilevel encoding scheme for transmitted data that encodes data in a multilevel code wherein the amplitude of any transition is always exactly one level during any time interval. A single-level transition between any two adjacent levels during a time interval represents a logical "1"; no transition during a time interval represents a logical "0". In a specific embodiment, modulation is limited to three defined amplitude levels equally space in amplitude and encoding is according to a three-level code. A four-bit to five-bit encoding scheme may be used to distribute bits for minimizing d.c. offset. The input data is preferably further scrambled to minimize aberrations in the emissions spectrum of signal carried over unshielded media.
摘要翻译：用于对多级代码中的数据进行编码的传输数据的多级编码方案，其中在任何时间间隔期间任何转换的幅度总是正好为一级。在一段时间间隔内任何两个相邻级别之间的单级转换代表逻辑“1”; 在时间间隔期间没有转换代表逻辑“0”。在一个具体实施例中，调制被限制在三个定义的振幅水平上，幅度上相等的空间，并且根据三电平码进行编码。可以使用四位到五位编码方案来分配比特以最小化直流。抵消。输入数据优选进一步加扰以最小化在非屏蔽介质上携带的信号的发射光谱中的像差。

26. 发明授权

US08788873B2 Server input/output failover device serving highly available virtual devices 有权
标题翻译：服务器输入/输出故障切换设备提供高可用性的虚拟设备
公开(公告)号：US08788873B2
公开(公告)日：2014-07-22
申请号：US13086595
申请日：2011-04-14
申请人： Michael B. Galles , Luca Cafiero
发明人： Michael B. Galles , Luca Cafiero
IPC分类号： G06F11/00
CPC分类号： G06F11/2005 , G06F13/4022 , G06F2201/815
摘要： A failover input/output device and corresponding method are provided to manage failover events of input/output controller devices that operate in accordance with a computer expansion card standard, such as the Peripheral Component Interconnect Express (PCIe) standard. The failover input/output device connects to redundant first and second virtualized input/output controller devices each comprising multiple virtual network interfaces that are in an active or standby state at any given time, and to a computing device that hosts one or more processes. The failover input/output device broadcasts transactions in accordance with the computer expansion card standard initiated from the computing device to the first and second virtualized input/output controller devices. The failover input/output device receives signals associated with upstream transaction completions in accordance with the computer expansion card standard for both active and standby virtual network interfaces on the first and second virtualized input/output controller devices. The failover input/output device forwards signals associated with upstream transaction completions for active virtual network interfaces on the first and second virtualized input/output controller devices to the computing device.
摘要翻译：提供故障切换输入/输出设备和相应的方法来管理根据计算机扩展卡标准操作的输入/输出控制器设备的故障切换事件，例如外围组件互连Express（PCIe）标准。故障切换输入/输出设备连接到冗余的第一和第二虚拟化输入/输出控制器设备，每个包括在任何给定时间处于活动或待机状态的多个虚拟网络接口以及托管一个或多个进程的计算设备。故障切换输入/输出设备根据从计算设备发起到第一和第二虚拟化输入/输出控制器设备的计算机扩展卡标准广播事务。故障切换输入/输出设备根据用于第一和第二虚拟化输入/输出控制器设备上的主动和备用虚拟网络接口的计算机扩展卡标准，接收与上游事务完成相关联的信号。故障切换输入/输出设备将与第一和第二虚拟化输入/输出控制器设备上的主动虚拟网络接口的上游事务完成相关联的信号转发到计算设备。

27. 发明申请

US20130081012A1 Storage drive virtualization 有权
公开(公告)号：US20130081012A1
公开(公告)日：2013-03-28
申请号：US13200281
申请日：2011-09-22
申请人： Satya Nishtala , Luca Cafiero
发明人： Satya Nishtala , Luca Cafiero
IPC分类号： G06F9/44
CPC分类号： G06F3/0605 , G06F3/0608 , G06F3/0665 , G06F3/067 , H04L67/1097
摘要： In one embodiment, a method includes defining a plurality of virtual drives in a physical drive in communication with a plurality of servers, assigning virtualization parameters to each of the virtual drives, and communicating the virtualization parameters to a drive manager located at the physical drive and operable to configure the virtual drives on the physical drive. An apparatus is also disclosed.

28. 发明申请

US20110222402A1 ETHERNET EXTENSION FOR THE DATA CENTER 有权
标题翻译：以太网扩展数据中心
公开(公告)号：US20110222402A1
公开(公告)日：2011-09-15
申请号：US13112824
申请日：2011-05-20
申请人： Silvano Gai , Thomas Edsall , Luca Cafiero , Davide Bergamasco , Dinesh Dutt , Flavio Bonomi
发明人： Silvano Gai , Thomas Edsall , Luca Cafiero , Davide Bergamasco , Dinesh Dutt , Flavio Bonomi
IPC分类号： H04L12/28 , H04L12/24
CPC分类号： H04L12/4633 , H04L12/4641 , H04L47/10 , H04L47/13 , H04L47/24 , H04L47/266 , H04L47/32 , H04L47/39 , H04L69/22
摘要： The present invention provides methods and devices for implementing a Low Latency Ethernet (“LLE”) solution, also referred to herein as a Data Center Ethernet (“DCE”) solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes (“VLs”) in a single physical connection of a data center or similar network. Some VLs are “drop” VLs, with Ethernet-like behavior, and others are “no-drop” lanes with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs.
摘要翻译：本发明提供了用于实现低延迟以太网（“LLE”）解决方案的方法和设备，这也被称为数据中心以太网（“DCE”）解决方案，其简化了数据中心的连接性并提供了高带宽，低用于承载以太网和存储流量的延迟网络。本发明的一些方面涉及将FC帧变换成适于在以太网上传输的格式。本发明的一些优选实现在数据中心或类似网络的单个物理连接中实现多个虚拟通道（“VL”）。一些VL是“下降”VL，具有类似以太网的行为，而其他VL是类似FC的行为的“不丢弃”通道。本发明的一些优选实施方案提供了基于信用和VL的保证带宽。使用小帧缓冲区时，主动缓冲区管理可实现高可靠性和低延迟。优选地，用于主动缓冲器管理的规则对于丢弃和不丢弃VL是不同的。

29. 发明授权

US07564869B2 Fibre channel over ethernet 有权
标题翻译：以太网上的光纤通道
公开(公告)号：US07564869B2
公开(公告)日：2009-07-21
申请号：US11078992
申请日：2005-03-10
申请人： Luca Cafiero , Silvano Gai
发明人： Luca Cafiero , Silvano Gai
IPC分类号： H04J3/26
CPC分类号： H04L47/522 , H04L12/4625 , H04L61/106 , H04L61/6022 , H04L61/6045
摘要： The present invention provides methods and devices for implementing a Low Latency Ethernet (“LLE”) solution, also referred to herein as a Data Center Ethernet (“DCE”) solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes (“VLs”) in a single physical connection of a data center or similar network. Some VLs are “drop” VLs, with Ethernet-like behavior, and others are “no-drop” lanes with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs.
摘要翻译：本发明提供了用于实现低延迟以太网（“LLE”）解决方案的方法和设备，这也被称为数据中心以太网（“DCE”）解决方案，其简化了数据中心的连接性并提供了高带宽，低用于承载以太网和存储流量的延迟网络。本发明的一些方面涉及将FC帧变换成适于在以太网上传输的格式。本发明的一些优选实现在数据中心或类似网络的单个物理连接中实现多个虚拟通道（“VL”）。一些VL是“下降”VL，具有类似以太网的行为，而其他VL是类似FC的行为的“不丢弃”通道。本发明的一些优选实施方案提供了基于信用和VL的保证带宽。使用小帧缓冲区时，主动缓冲区管理可实现高可靠性和低延迟。优选地，用于主动缓冲器管理的规则对于丢弃和不丢弃VL是不同的。

30. 发明申请

US20090177861A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177861A1
公开(公告)日：2009-07-09
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F9/34
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

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