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21. 发明申请

US20130145202A1 Handling Virtual-to-Physical Address Translation Failures 审中-公开
标题翻译：处理虚拟到物理地址转换失败
公开(公告)号：US20130145202A1
公开(公告)日：2013-06-06
申请号：US13311822
申请日：2011-12-06
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas R. Woller , Sebastien Nussbaum , Rex McCrary , Philip J. Rogers , Mark Leather
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas R. Woller , Sebastien Nussbaum , Rex McCrary , Philip J. Rogers , Mark Leather
IPC分类号： G06F11/07
CPC分类号： G06F12/1027 , G06F12/1081
摘要： A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed.
摘要翻译：一种方法允许虚拟到物理地址转换失败。翻译请求从图形处理装置发送到翻译机构。翻译请求与第一个波前相关联。在来自转换机制的加速处理设备（APD）中接收到不能确认请求的故障通知。如果接收到故障通知，第一个波阵面存储在APD的着色器核心内。如果接收到故障通知，则第一个波前被替换为第二个波阵面，第二个波阵面准备好执行。

22. 发明授权

US08803891B2 Method for preempting graphics tasks to accommodate compute tasks in an accelerated processing device (APD) 有权
标题翻译：用于抢占图形任务以适应加速处理设备（APD）中的计算任务的方法
公开(公告)号：US08803891B2
公开(公告)日：2014-08-12
申请号：US13307904
申请日：2011-11-30
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Sebastien Nussbaum , Rex McCrary , Mark Leather , Philip J. Rogers , Thomas R. Woller
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Sebastien Nussbaum , Rex McCrary , Mark Leather , Philip J. Rogers , Thomas R. Woller
IPC分类号： G06F9/46
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887
摘要： Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria.
摘要翻译：本文描述的实施例提供了一种仲裁处理资源的方法。该方法包括接收用于抢占任务并防止与该任务相关联的附加波前处理的命令。该方法还包括基于预定标准来驱逐与该任务相关联的当前正在执行的波前处理。

23. 发明申请

US20120194527A1 Method for Preempting Graphics Tasks to Accommodate Compute Tasks in an Accelerated Processing Device (APD) 有权
标题翻译：用于抢占图形任务来容纳加速处理设备（APD）中的计算任务的方法
公开(公告)号：US20120194527A1
公开(公告)日：2012-08-02
申请号：US13307904
申请日：2011-11-30
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Sebastien Nussbaum , Rex McCrary , Mark Leather , Philip J. Rogers , Thomas R. Woller
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Sebastien Nussbaum , Rex McCrary , Mark Leather , Philip J. Rogers , Thomas R. Woller
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887
摘要： Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria
摘要翻译：本文描述的实施例提供了一种仲裁处理资源的方法。该方法包括接收用于抢占任务并防止与该任务相关联的附加波前处理的命令。该方法还包括基于预定标准来驱逐与该任务相关联的当前正在执行的波前处理

24. 发明申请

US20130141447A1 Method and Apparatus for Accommodating Multiple, Concurrent Work Inputs 审中-公开
标题翻译：用于容纳多个并发工作输入的方法和装置
公开(公告)号：US20130141447A1
公开(公告)日：2013-06-06
申请号：US13311830
申请日：2011-12-06
申请人： Robert Scott Hartog , Mark Leather , Michael Mantor , Rex McCrary , Sebastien Nussbaum , Philip Rogers , Ralph Clay Taylor , Thomas Woller
发明人： Robert Scott Hartog , Mark Leather , Michael Mantor , Rex McCrary , Sebastien Nussbaum , Philip Rogers , Ralph Clay Taylor , Thomas Woller
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list.
摘要翻译：提供了一种容纳多个计算输入的方法。该方法创建一个APD仲裁策略，其将等待处理的指令序列的计算指令动态地分配给用于执行运行列表的APD计算单元。

25. 发明授权

US08933942B2 Partitioning resources of a processor 有权
标题翻译：分配处理器的资源
公开(公告)号：US08933942B2
公开(公告)日：2015-01-13
申请号：US13315121
申请日：2011-12-08
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas Roy Woller , Kevin McGrath , Rex McCrary , Philip J. Rogers , Mark Leather
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas Roy Woller , Kevin McGrath , Rex McCrary , Philip J. Rogers , Mark Leather
IPC分类号： G06F15/16 , G06T1/00 , G06F9/46 , G06F9/50
CPC分类号： G06F9/505 , G06F2209/509
摘要： Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold.
摘要翻译：本文描述的实施例提供了一种用于同时处理APD内的任务的装置，计算机可读介质和方法。该方法包括处理APD内的第一任务。该方法还包括通过第一任务降低APD的利用率，以促进第二任务的同时处理，使得利用率保持低于阈值。

26. 发明授权

US08281183B2 Apparatus with redundant circuitry and method therefor 有权
标题翻译：具有冗余电路的装置及其方法
公开(公告)号：US08281183B2
公开(公告)日：2012-10-02
申请号：US12509803
申请日：2009-07-27
申请人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
发明人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译：具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。冗余的并行ALU然后对有缺陷的ALU进行操作。输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于由其他电路进一步处理。

27. 发明授权

US08854381B2 Processing unit that enables asynchronous task dispatch 有权
标题翻译：启用异步任务调度的处理单元
公开(公告)号：US08854381B2
公开(公告)日：2014-10-07
申请号：US12874134
申请日：2010-09-01
申请人： Michael Mantor , Rex McCrary
发明人： Michael Mantor , Rex McCrary
IPC分类号： G06F15/80 , G06F15/16 , G06F9/50 , G06T15/00 , G06T1/20
CPC分类号： G06F9/5027 , G06F9/5061 , G06F9/5066 , G06F2209/5017 , G06T1/20 , G06T15/005
摘要： A processing unit that includes a plurality of virtual engines and a shader core. The plurality of virtual engines is configured to (i) receive, from an operating system (OS), a plurality of tasks substantially in parallel with each other and (ii) load a set of state data associated with each of the plurality of tasks. The shader core is configured to execute the plurality of tasks substantially in parallel based on the set of state data associated with each of the plurality of tasks. The processing unit may also include a scheduling module that schedules the plurality of tasks to be issued to the shader core.
摘要翻译：一种包括多个虚拟引擎和着色器核心的处理单元。多个虚拟引擎被配置为（i）从操作系统（OS）接收基本上彼此并行的多个任务，以及（ii）加载与所述多个任务中的每一个相关联的一组状态数据。着色器核心被配置为基于与多个任务中的每一个相关联的一组状态数据来执行大量并行的多个任务。处理单元还可以包括调度模块，其调度要发布到着色器核心的多个任务。

28. 发明授权

US06728869B1 Method and apparatus for memory latency avoidance in a processing system 有权
标题翻译：处理系统中的内存延迟回避的方法和装置
公开(公告)号：US06728869B1
公开(公告)日：2004-04-27
申请号：US09556471
申请日：2000-04-21
申请人： Michael Andrew Mang , Michael Mantor , Robert Scott Hartog
发明人： Michael Andrew Mang , Michael Mantor , Robert Scott Hartog
IPC分类号： G06F9312
CPC分类号： G06F9/3001 , G06F9/30101 , G06F9/3826 , G06F9/3851
摘要： A method and apparatus for avoiding latency in a processing system that includes a memory for storing intermediate results is presented. The processing system stores results produced by an operation unit in memory, where the results may be used by subsequent dependent operations. In order to avoid the latency of the memory, the output for the operation unit may be routed directly back into the operation unit as a subsequent operand. Furthermore, one or more memory bypass registers are included such that the results produced by the operation unit during recent operations that have not yet satisfied the latency requirements of the memory are also available. A first memory bypass register may thus provide the result of an operation that completed one cycle earlier, a second memory bypass register may provide the result of an operation that completed two cycles earlier, etc.
摘要翻译：提出了一种用于在包括用于存储中间结果的存储器的处理系统中避免等待时间的方法和装置。处理系统将由操作单元产生的结果存储在存储器中，其中结果可以由随后的依赖操作使用。为了避免存储器的等待时间，操作单元的输出可以作为后续操作数直接返回到操作单元中。此外，包括一个或多个存储器旁路寄存器，使得操作单元在最近操作期间产生的尚未满足存储器的等待时间要求的结果也是可用的。因此，第一存储器旁路寄存器可以提供更早完成一个周期的操作的结果，第二存储器旁路寄存器可以提供早于两个周期完成的操作的结果等。

29. 发明授权

US07577869B2 Apparatus with redundant circuitry and method therefor 有权
标题翻译：具有冗余电路的装置及其方法
公开(公告)号：US07577869B2
公开(公告)日：2009-08-18
申请号：US11161672
申请日：2005-08-11
申请人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
发明人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译：具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。冗余的并行ALU然后对有缺陷的ALU进行操作。输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于由其他电路进一步处理。

30. 发明申请

US20100017652A1 APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR 有权
标题翻译：具有冗余电路的装置及其方法
公开(公告)号：US20100017652A1
公开(公告)日：2010-01-21
申请号：US12509803
申请日：2009-07-27
申请人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
发明人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
IPC分类号： G06F11/20
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译：具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。冗余的并行ALU然后对有缺陷的ALU进行操作。输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于由其他电路进一步处理。

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