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21. 发明授权

US4713678A dRAM cell and method 失效
标题翻译： dRAM单元格和方法
公开(公告)号：US4713678A
公开(公告)日：1987-12-15
申请号：US928717
申请日：1986-11-13
申请人： Richard H. Womack , Sanjay K. Banerjee , Hisashi Shichijo , Satwinder Malhi
发明人： Richard H. Womack , Sanjay K. Banerjee , Hisashi Shichijo , Satwinder Malhi
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/06
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.
摘要翻译：公开了一种dRAM单元和单元阵列以及一种制造方法，其中单元包括一个场效应晶体管和一个存储电容器，其中电容器形成在衬底中的沟槽中，并且晶体管沟道通过外延生长在衬底上形成。晶体管源极和漏极与衬底绝缘，并且晶体管可以与沟槽或沟槽侧壁的上部相邻。信号电荷存储在与基板绝缘的电容器板上。

22. 发明授权

US4545034A Contactless tite RAM 失效
标题翻译：非接触式内存
公开(公告)号：US4545034A
公开(公告)日：1985-10-01
申请号：US505157
申请日：1983-06-17
申请人： Pallab Chatterjee , Hisashi Shichijo , John E. Leiss
发明人： Pallab Chatterjee , Hisashi Shichijo , John E. Leiss
IPC分类号： G11C11/401 , G11C11/403 , G11C14/00 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/788 , G11C11/40
CPC分类号： H01L29/7881 , G11C11/403
摘要： A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.
摘要翻译：横向注入的准浮动存储单元。体硅中的存储晶体管具有体硅中的沟道区，其电容耦合到薄多晶硅准浮置栅极和上覆字线。包括浮置栅极的薄多晶硅层与存储晶体管的沟道区域不相邻，但是薄多晶硅层的准浮置栅极部分通过多晶硅沟道区域连接到写入位线。因此，叠加字线对于薄多晶硅层中的写入晶体管以及衬底中的存储晶体管本身也是如此。

23. 发明授权

US08134204B2 DEMOS transistors with STI and compensated well in drain 有权
标题翻译： DEMOS晶体管采用STI，并在漏极中良好补偿
公开(公告)号：US08134204B2
公开(公告)日：2012-03-13
申请号：US12536810
申请日：2009-08-06
申请人： Kamel Benaissa , Hisashi Shichijo
发明人： Kamel Benaissa , Hisashi Shichijo
IPC分类号： H01L27/088
CPC分类号： H01L21/823814 , H01L27/092 , H01L27/0922 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0869 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/456 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without adding any process steps. Both n-channel and p-channel versions may be fabricated in CMOS ICs with an n-type buried layer. Furthermore, the inventive transistor may be fabricated in an IC built in an SOI wafer. The width of the compensation region may be varied across multiple instances of the inventive DEMOS transistor to provide a capability for handling multiple signals with different voltage levels in the same IC without adding fabrication steps. The compensation region may be biased by a control voltage to modulate the depletion of the drain extension and provide a capability for handling multiple signal voltage levels in a single transistor.
摘要翻译：公开了一种漏极扩展MOS（DEMOS）晶体管，其具有将漏极接触与栅极分离的场氧化物的元素，以及栅极下的漏极中具有相反极性的补偿区域。本发明的DEMOS可以在CMOS IC中制造而不添加任何工艺步骤。可以在具有n型掩埋层的CMOS IC中制造n沟道和p沟道版本。此外，本发明的晶体管可以制造在内置于SOI晶片中的IC中。补偿区域的宽度可以在本发明的DEMOS晶体管的多个实例上变化，以提供在同一IC中处理具有不同电压电平的多个信号的能力，而无需添加制造步骤。可以通过控制电压来补偿补偿区域，以调制漏极延伸的耗尽，并提供处理单个晶体管中的多个信号电压电平的能力。

24. 发明授权

US07719299B2 Process and temperature insensitive flicker noise monitor circuit 有权
标题翻译：过程和温度不敏感的闪烁噪声监测电路
公开(公告)号：US07719299B2
公开(公告)日：2010-05-18
申请号：US12061409
申请日：2008-04-02
申请人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
发明人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
IPC分类号： G01R31/02 , H01L21/66
CPC分类号： H03M3/35 , H01L22/34 , H03M3/43 , H03M3/438
摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.
摘要翻译：在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。数字信号以可配置的时间间隔存储以形成数字比特流。将数字位流与参考值进行比较，以确定缺陷是否在允许范围内。

25. 发明授权

US07692217B2 Matched analog CMOS transistors with extension wells 有权
标题翻译：具有扩展阱的匹配模拟CMOS晶体管
公开(公告)号：US07692217B2
公开(公告)日：2010-04-06
申请号：US11948172
申请日：2007-11-30
申请人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
发明人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
IPC分类号： H01L27/148
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及集成电路。集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。还公开了其他装置，方法和系统。

26. 发明授权

US06512280B2 Integrated CMOS structure for gate-controlled buried photodiode 有权
公开(公告)号：US06512280B2
公开(公告)日：2003-01-28
申请号：US09859121
申请日：2001-05-16
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L31072
CPC分类号： H01L31/112 , H01L27/1463 , H01L27/148
摘要： A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

27. 发明授权

US5290719A Method of making complementary heterostructure field effect transistors 失效
标题翻译：制备互补异质结场效应晶体管的方法
公开(公告)号：US5290719A
公开(公告)日：1994-03-01
申请号：US956132
申请日：1992-10-02
申请人： Han-Tzong Yuan , Hisashi Shichijo , Hung-Dah Shih
发明人： Han-Tzong Yuan , Hisashi Shichijo , Hung-Dah Shih
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/095 , H01L29/43 , H01L29/778 , H01L21/265
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/095 , H01L29/432 , H01L29/7786 , Y10S148/072
摘要： Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.
摘要翻译：公开了具有互补栅极（40,50）和阈值调节掺杂的互补器件的互补异质结构场效应晶体管（30）。优选实施例的器件包括由掺杂剂扩散形成的p +栅极（50），以将n +栅极材料转换为p +，以及与二维载气通道相邻的脉冲掺杂层以调整阈值电压。进一步优选的实施例具有包含未转换的n +的残留层的导电型转换栅极（50），其与脉冲掺杂层阈值移位配合，以产生对n沟道小且为正的阈值电压，通道设备。

28. 发明授权

US5214298A Complementary heterostructure field effect transistors 失效
标题翻译：互补异质结场场效应晶体管
公开(公告)号：US5214298A
公开(公告)日：1993-05-25
申请号：US582818
申请日：1990-09-14
申请人： Han-Tzong Yuan , Hisashi Shichijo , Hung-Dah Shih
发明人： Han-Tzong Yuan , Hisashi Shichijo , Hung-Dah Shih
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/095 , H01L29/43 , H01L29/778
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/095 , H01L29/432 , H01L29/7786 , Y10S148/072
摘要： Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.
摘要翻译：公开了具有互补栅极（40,50）和阈值调整掺杂的互补器件的互补异质结构场效应晶体管（30）。优选实施例的器件包括通过掺杂剂的扩散将n +栅极材料转化为p +形成的p +栅极（50）以及邻近二维载气通道的脉冲掺杂层以调整阈值电压。进一步优选的实施例具有包含未转换的n +的残留层的导电型转换栅极（50），其与脉冲掺杂层阈值移位配合，以产生对n沟道为小且为正的阈值电压，对于p- 通道设备。

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