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21. 发明授权

US4589092A Data buffer having separate lock bit storage array 失效
标题翻译：数据缓冲区具有单独的锁定位存储阵列
公开(公告)号：US4589092A
公开(公告)日：1986-05-13
申请号：US560479
申请日：1983-12-12
申请人： Richard E. Matick
发明人： Richard E. Matick
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/145
摘要： A separate lock bit array (LBA) is provided in combination with a translation lookaside buffer (TLB) in a data processing system such that the lock bits are stored in and accessed from the LBA. A segment register with a portion for an "S" bit is included and when S=1, a translation operation for the lock bits is performed in parallel with the TLB accessing by use and operation of the LBA. In such operation, when S=1, lower order virtual bits from a central processing unit (CPU) address register are applied to the LBA to select one of the rows of the LBA which consists of virtual address bits and lock bits. Segment identification bits from the segment register are combined with virtual bits from the CPU address register and are applied to first and second compare circuits. If there is a match in the first compare circuit with a first group of virtual bits from an LBA location, a first flag signal is generated and applied to a gate circuit to gate out a first associated group of lock bits from a first location. Likewise, the combination of bits are compared with VA'.sub.b bits in the second compare circuit, and if a match occurs in the second compare circuit, a second flag signal is produced which is applied to a gate to gate out a second associated group of lock bits from a second location of the LBA.
摘要翻译：与数据处理系统中的翻译后备缓冲器（TLB）组合提供单独的锁定位阵列（LBA），使得锁定位被存储在LBA中并从LBA访问。包括具有“S”位的部分的段寄存器，当S = 1时，通过LBA的使用和操作与TLB访问并行地执行锁定位的转换操作。在这种操作中，当S = 1时，来自中央处理单元（CPU）地址寄存器的低阶虚拟位被应用于LBA以选择由虚拟地址位和锁定位组成的LBA中的一行。来自段寄存器的段识别位与来自CPU地址寄存器的虚拟位组合并应用于第一和第二比较电路。如果在第一比较电路中与来自LBA位置的第一组虚拟位相匹配，则生成第一标志信号并将其施加到门电路以从第一位置门出第一相关锁定位组。类似地，将比特组合与第二比较电路中的VA'b比较，并且如果在第二比较电路中发生匹配，则产生第二标志信号，其被施加到门以选出第二相关组从LBA的第二个位置锁定位。

22. 发明授权

US4287575A High speed high density, multi-port random access memory cell 失效
标题翻译：高速高密度，多端口随机存取存储单元
公开(公告)号：US4287575A
公开(公告)日：1981-09-01
申请号：US108070
申请日：1979-12-28
申请人： David B. Eardley , Richard E. Matick
发明人： David B. Eardley , Richard E. Matick
IPC分类号： G11C11/414 , G11C8/16 , G11C11/411 , G11C11/40
CPC分类号： G11C8/16 , G11C11/4113
摘要： A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells, each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors have their emitters connected to the respective control nodes of the static cell, their bases connected to first and second word lines, and their collectors connected to first and second bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells of a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.
摘要翻译：公开了一种随机存取存储器系统，其中存储在由不同地址信号定义的两个不同存储器位置中的数据可以同时非破坏性地读出。该系统采用双端口存储器单元的矩阵，每个单元用于在传统的交叉耦合公共发射极触发器中存储一个二进制数据位。一对输入/输出晶体管的发射极连接到静态单元的各个控制节点，它们的基极连接到第一和第二字线，它们的集电极连接到第一和第二位感测线。字线和位线被寻址和脉冲，使得在读取所选择的单元期间，电流仅流过感测线的单元中的一个的输入晶体管中，在写入期间，电流流过输入/ 输出晶体管，写入期间电流的方向取决于存储的二进制位的值。与每个单元相关联的输入/输出晶体管被集成到芯片上并且占据比现有技术的双端口单元中常规使用的多配置器件稍微更多的面积。

23. 发明授权

US4663729A Display architecture having variable data width 失效
标题翻译：具有可变数据宽度的显示架构
公开(公告)号：US4663729A
公开(公告)日：1987-05-05
申请号：US616047
申请日：1984-06-01
申请人： Richard E. Matick , Daniel T. Ling , Frederick H. Dill
发明人： Richard E. Matick , Daniel T. Ling , Frederick H. Dill
IPC分类号： G09G5/00 , G06F3/153 , G06F5/01 , G09G5/39 , G09G5/391 , G09G5/395 , G06F13/00
CPC分类号： G09G5/391 , G06F5/01 , G09G5/39
摘要： A display architecture is disclosed which supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X.sub.o, Y.sub.o, the data path width N.sub.D and an encoded segment width S. A bit incrementer in the function generator generates increment bits A.sub.I based on the externally supplied modulo N.sub.D. The function generator generates the physical word address w.sub.o and physical bit address b.sub.o based on the starting address X.sub.o, Y.sub.o, the data path width N.sub.D and the encoded segment width S. Logic circuitry is provided which is responsive to an overflow bit produced by the bit incrementer to control spill and wrap functions. Spill results from the usual bit address incrementing where the data spills from the highest order chip to the lowest. Wrap is a special case when spill occurs at the right hand edge of the screen and data wraps around on the same scan line to the left hand edge of the screen.
摘要翻译：公开了一种显示架构，其支持每个芯片的可变的，可选择的位数和可变的可选择的段宽度。该架构包括多个动态存储器芯片和功能发生器。每个存储器芯片包括至少两个数据岛，其中每个数据岛具有其自身的数据输入/输出，由功能发生器提供的片选和递增位。函数发生器接收起始地址Xo，Yo，数据路径宽度ND和编码段宽度S.函数发生器中的位增量器基于外部提供的模ND产生增量位AI。函数发生器基于起始地址Xo，Yo，数据路径宽度ND和编码段宽度S生成物理字地址wo和物理位地址bo。提供响应于由位产生的溢出位的逻辑电路增量器来控制溢出和包装功能。从数据溢出从最高订单芯片到最低位的通常的位地址递增溢出结果。包装是在屏幕右侧边缘发生溢出的特殊情况，并且数据在同一扫描线周围卷绕到屏幕的左侧边缘。

24. 发明授权

US4649516A Dynamic row buffer circuit for DRAM 失效
标题翻译： DRAM的动态行缓冲电路
公开(公告)号：US4649516A
公开(公告)日：1987-03-10
申请号：US616045
申请日：1984-06-01
申请人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
发明人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
IPC分类号： G11C11/401 , G06F12/00 , G11C7/10 , G11C11/4093 , G06F13/38
CPC分类号： G11C7/106 , G11C11/4093 , G11C7/1051 , G11C7/1075
摘要： A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
摘要翻译：公开了用于动态随机存取存储器（DRAM）芯片的动态行缓冲器电路，其使DRAM芯片能够用于特殊功能应用。动态行缓冲器包括行缓冲器主寄存器和行缓冲器从寄存器。行缓冲器主寄存器包括多个主电路（M1）和多个从电路（S1）。类似地，行缓冲器从机寄存器包括多个主电路（M2）和多个从电路（S2）。行缓冲器主寄存器是并行负载并行读出，主寄存器从电路的输出端连接到从机寄存器的主电路。行缓冲器从寄存器是一个并行负载，串行读出寄存器，输出端从辅助输出端口移出。整个行缓冲器可以与存储器阵列隔离，并且当这样隔离时，存储器阵列可以以与普通DRAM芯片相同的方式通过主输入/输出端口访问。这种布置允许将DRAM芯片转换为双端口显示器，其中公开了一个具体示例，或者一些其他特殊功能RAM，从而以少量额外成本为DRAM芯片增加了大的价值。

25. 发明授权

US4616310A Communicating random access memory 失效
标题翻译：通信随机存取存储器
公开(公告)号：US4616310A
公开(公告)日：1986-10-07
申请号：US496726
申请日：1983-05-20
申请人： Frederick H. Dill , Daniel T. Ling , Richard E. Matick , Dennis J. McBride
发明人： Frederick H. Dill , Daniel T. Ling , Richard E. Matick , Dennis J. McBride
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08 , G06F13/38 , G06F15/167 , G06F15/16 , G11C7/00
CPC分类号： G06F15/167 , G06F12/0813
摘要： A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer connected in between the first and second bit arrays on each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A controller is located on each chip and connected to the first and second memory arrays and the M bit buffer for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.
摘要翻译：用于多处理器系统的通信随机存取共享存储器配置被连接到处理器以在处理器之间传送数据。随机存取存储器配置包括多个互连的随机存取存储器芯片，这些存储器芯片中的每一个包括第一和第二分离存储器位阵列，其具有M位长度的N字存储位置，M位缓冲器连接在第一和第二位阵列之间在每个存储器芯片上，以及连接到每个芯片上的第一和第二位阵列的第一和第二输入/输出端口，用于从芯片外部输入和从芯片移除数据。控制器位于每个芯片上并且连接到第一和第二存储器阵列以及M位缓冲器，用于在第一和第二存储器阵列之间传送数据并进入和离开第一和第二输入/输出端口。

26. 发明授权

US4577293A Distributed, on-chip cache 失效
标题翻译：分布式片上缓存
公开(公告)号：US4577293A
公开(公告)日：1986-03-18
申请号：US616046
申请日：1984-06-01
申请人： Richard E. Matick , Daniel T. Ling
发明人： Richard E. Matick , Daniel T. Ling
IPC分类号： G06F12/08 , G06F12/10 , G11C7/10 , G11C8/12 , G11C7/00
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/1063 , G11C7/1075 , G11C8/12
摘要： The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use of communicating random access memory chips of the type incorporating a primary port (10) and a secondary port (14). Ideally, the primary and secondary ports can run totally independently of each other. The primary port functions as in a typical dynamic random access memory and is the usual input/output path for the memory chips. The secondary port, which provides the distributed cache, makes use of a separate master/slave row buffer (15) which is normally isolated from the sense amplifier/latches. Once this master/slave row buffer is loaded, it can be accessed very fast, and the large bandwidth between the main memory array and the on-chip row buffer provides a very fast reload time for a cache miss.
摘要翻译：通过使用位于存储器芯片上的分布式缓存来提高小型计算机系统中的缓存重新加载时间。主存储器和高速缓存之间的大带宽是通常的片上互连线，避免了引脚输入/输出问题。通过使用包含主端口（10）和辅助端口（14）的类型的通信随机存取存储器芯片来实现该分布式高速缓存。理想情况下，主端口和辅助端口可以完全独立运行。主端口在典型的动态随机存取存储器中起作用，并且是用于存储器芯片的通常的输入/输出路径。提供分布式缓存的辅助端口使用通常与读出放大器/锁存器隔离的单独的主/从行行缓冲器（15）。一旦这个主/从行缓冲器被加载，它可以非常快速地访问，并且主存储器阵列和片上行缓冲器之间的大带宽为缓存未命中提供非常快的重新加载时间。

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