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    • 27. 发明授权
    • Cache subsystem with pseudo-packet switch
    • 具有伪分组交换的缓存子系统
    • US5974511A
    • 1999-10-26
    • US828470
    • 1997-03-31
    • Jayabharat BodduJui-Cheng Su
    • Jayabharat BodduJui-Cheng Su
    • G06F12/08G06F12/00
    • G06F12/0835G06F12/0811
    • A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus. However, if the snoop logic circuit does not find the physical address in the bus cache or finds that the data is invalid, the snoop logic circuit causes (1) the peripheral bus interface unit to perform a retry operation on the peripheral bus and (2) the cache controller to process a memory request to retrieve the requested data from the L1 cache, L2 cache (if any) or the main memory and store the requested data into the bus cache. In addition, when the device retries the memory read request, the bus cache will have the requested data so that the data can be immediately provided to the peripheral bus. Thus, in memory read transactions longer than a cache line, the data is provided on the peripheral bus in a pseudo-packet switched manner.
    • 主机包括总线缓存,L1高速缓存和增强型窥探逻辑电路,以在存储器访问事务期间增加外围总线的带宽。 当连接到外围总线的设备开始存储器读取事务时,主机将存储器读取事务的虚拟地址转换为物理地址。 侦听逻辑电路检查物理地址是否在总线缓存中,如果是,则对应于地址的总线缓存中的数据是否有效。 如果总线缓存命中,则从总线缓存访问相应的数据并输出到外设总线上。 然而,如果窥探逻辑电路没有在总线缓存中找到物理地址或发现数据无效,则侦听逻辑电路使(1)外围总线接口单元在外设总线上执行重试操作,(2 )高速缓存控制器来处理存储器请求以从L1高速缓存,L2高速缓存(如果有的话)或主存储器中检索所请求的数据,并将所请求的数据存储到总线缓存中。 此外,当设备重试存储器读取请求时,总线缓存将具有所请求的数据,使得可以将数据立即提供给外围总线。 因此,在高于高速缓存行的存储器读取事务中,以伪分组交换的方式在外围总线上提供数据。