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21. 发明申请

US20130027009A1 Switching Regulator with Increased Light Load Efficiency 有权
标题翻译：开关稳压器具有增加的轻负载效率
公开(公告)号：US20130027009A1
公开(公告)日：2013-01-31
申请号：US13194314
申请日：2011-07-29
申请人： Benjamim Tang , Amir Babazadeh , Giuseppe Bernacchia , Kenneth A. Ostrom
发明人： Benjamim Tang , Amir Babazadeh , Giuseppe Bernacchia , Kenneth A. Ostrom
IPC分类号： G05F1/00
CPC分类号： H02M3/158 , H02M3/1584 , H02M2001/0032 , Y02B70/16
摘要： A switching regulator includes a multiphase converter which includes a plurality of main phases configured to covert a power supply voltage to a lower voltage for application to an electronic device at different load conditions. The switching regulator also includes an auxiliary phase configured to operate in a pulse frequency modulation mode during a light load condition so that power is supplied to the electronic device by at least the auxiliary phase during the light load condition.
摘要翻译：开关调节器包括多相转换器，其包括多个主相，其配置为将电源电压转换为较低的电压，以在不同的负载条件下应用于电子设备。开关调节器还包括配置为在轻负载状态期间以脉冲频率调制模式操作的辅助相位，使得在轻负载状态期间至少辅助相位向电子设备供电。

22. 发明申请

US20120200274A1 MULTIPHASE POWER REGULATOR WITH ACTIVE TRANSIENT RESPONSE CIRCUITRY 有权
标题翻译：具有主动瞬态响应电路的多相功率调节器
公开(公告)号：US20120200274A1
公开(公告)日：2012-08-09
申请号：US13365908
申请日：2012-02-03
申请人： Benjamim Tang , Robert T. Carroll , Scott Wilson Southwell , Kenneth A. Ostrom , Richard C. Pierson
发明人： Benjamim Tang , Robert T. Carroll , Scott Wilson Southwell , Kenneth A. Ostrom , Richard C. Pierson
IPC分类号： G05F1/56
CPC分类号： H02M3/1584
摘要： A multiphase power regulator includes a multiphase pulse width modulator, an output stage and an active transient response circuit. The output stage includes a high side transistor, a low side transistor and an inductor. The output stage is configured to supply power to a load responsive to signals generated by the multiphase pulse width modulator. The active transient response circuit is coupled between the output stage and the multiphase pulse width modulator and configured to detect the voltage level at the output stage and provide a signal to the multiphase pulse width modulator that is a function of the amplitude of the deviation of the detected voltage level from a target voltage.
摘要翻译：多相功率调节器包括多相脉宽调制器，输出级和有源瞬态响应电路。输出级包括高侧晶体管，低侧晶体管和电感器。输出级被配置为响应于由多相脉宽调制器产生的信号向负载供电。有源瞬态响应电路耦合在输出级和多相脉宽调制器之间，并被配置为检测输出级的电压电平，并向多相脉宽调制器提供信号，该信号是幅度偏差的函数从目标电压检测电压电平。

23. 发明申请

US20090224733A1 METHODS AND APPARATUS FOR A POWER SUPPLY 有权
标题翻译：电源的方法和装置
公开(公告)号：US20090224733A1
公开(公告)日：2009-09-10
申请号：US12043261
申请日：2008-03-06
申请人： Benjamim Tang , Laura Carpenter , Kenneth A. Ostrom
发明人： Benjamim Tang , Laura Carpenter , Kenneth A. Ostrom
IPC分类号： G05F1/00
CPC分类号： H02M3/158 , H02M1/08 , H02M1/088 , H02M3/156 , H02M3/1584 , H02M2001/0048
摘要： Methods and apparatus for a power supply according various aspects of the present invention operate in conjunction with a voltage converter for converting an input voltage to an output voltage. For example, the converter may comprise an output controller configured to generate a control signal, a power mode controller, and an integrated power stage. The power stage may include a multiple switch segments coupled in parallel between the input voltage and the output, and a driver circuit responsive to the output controller and the power mode controller and connected to the switch segments. The driver circuit controls the switch segments according to the control signal to activate the switch segments in the switch circuit. The driver circuit also disables one or more of the switch segments according to the power mode signal to permit reduced power delivery and demand states.
摘要翻译：电源的方法和装置根据本发明的各个方面与用于将输入电压转换成输出电压的电压转换器一起工作。例如，转换器可以包括被配置为产生控制信号的输出控制器，功率模式控制器和集成功率级。功率级可以包括在输入电压和输出之间并联耦合的多个开关段，以及响应于输出控制器和功率模式控制器并连接到开关段的驱动器电路。驱动器电路根据控制信号控制开关段，以激活开关电路中的开关段。驱动器电路还根据功率模式信号禁用一个或多个开关段，以允许减少功率输送和需求状态。

24. 发明授权

US07194059B2 Method and apparatus for skip-free retiming transmission of digital information 有权
标题翻译：数字信息的无跳跃重新定时传输的方法和装置
公开(公告)号：US07194059B2
公开(公告)日：2007-03-20
申请号：US10223842
申请日：2002-08-19
申请人： Brian Wong , Benjamim Tang , Scott Southwell , Allen Sakai
发明人： Brian Wong , Benjamim Tang , Scott Southwell , Allen Sakai
IPC分类号： H04L23/00
CPC分类号： H04L25/242
摘要： A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.
摘要翻译：描述了一种用于在同步数据通信系统中传输数字信息的无跳越重定时系统和方法。该系统能够在第一和最后一个节点之间的串行数据路径中支持无限数量的重新定时器。重新配置配置用于重新计算，放大和重传接收的数据流，而不改变接收到的数据速率。因此，来自第一节点的数据速率在最后一个节点处以相同的频率被接收，而不管重定时器的数量如何。通常，重定时器在重定时器本地时钟而不是在数据流上执行速率补偿，因此干净的重新定时器时钟的属性可以应用于数据流而不改变数据速率。

25. 发明申请

US20060001408A1 Digital calibration with lossless current sensing in a multiphase switched power converter 有权
标题翻译：在多相开关电源转换器中进行无损耗电流检测的数字校准
公开(公告)号：US20060001408A1
公开(公告)日：2006-01-05
申请号：US10884840
申请日：2004-07-02
申请人： Scott Southwell , Benjamim Tang , Robert Carroll , Steven Schulte
发明人： Scott Southwell , Benjamim Tang , Robert Carroll , Steven Schulte
IPC分类号： G05F1/40
CPC分类号： H02M3/1584 , H02M2001/0009
摘要： Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a known calibration current at the load and determining actual current values by the difference in measured values between when the known calibration current is applied and when it is not applied. The accurate current is determined at a known temperature and accurate temperature compensation is provided by a non-linear digital technique. Each phase of the multi-phase power regulator is individually calibrated so that balanced channels provide accurate power to the load. Also disclosed is a calibration method with minimal noise generation.
摘要翻译：公开了一种多相功率调节器，其以无损耗的方式精确地感测负载处的电流，并且基于感测的电流来调节提供给负载的功率。还公开了一种通过在负载处施加已知的校准电流并且通过施加已知校准电流之间的测量值和当不施加已知校准电流时的测量值的差来确定实际电流值来校准多相电压调节器的方法。在已知温度下确定精确电流，并通过非线性数字技术提供精确的温度补偿。单相校准多相功率调节器的每相，以便平衡通道为负载提供精确的功率。还公开了一种具有最小噪声产生的校准方法。

26. 发明授权

US08239579B2 PLL/DLL dual loop data synchronization 有权
标题翻译： PLL / DLL双循环数据同步
公开(公告)号：US08239579B2
公开(公告)日：2012-08-07
申请号：US12719450
申请日：2010-03-08
申请人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
发明人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： G06F15/16
CPC分类号： H04J3/047 , H04J3/062 , H04J3/0685 , H04L7/033
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，而不是本地引用。因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

27. 发明授权

US07743168B2 PLL/DLL dual loop data synchronization 有权
标题翻译： PLL / DLL双循环数据同步
公开(公告)号：US07743168B2
公开(公告)日：2010-06-22
申请号：US12077002
申请日：2008-03-14
申请人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
发明人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： G06F15/16
CPC分类号： H04J3/047 , H04J3/062 , H04J3/0685 , H04L7/033
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，而不是本地引用。因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

28. 发明授权

US08049482B2 Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators 有权
公开(公告)号：US08049482B2
公开(公告)日：2011-11-01
申请号：US12969366
申请日：2010-12-15
申请人： Benjamim Tang , Robert T. Carroll , Scott Southwell
发明人： Benjamim Tang , Robert T. Carroll , Scott Southwell
IPC分类号： G05F1/575
CPC分类号： H02M3/1584
摘要： Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected.

29. 发明申请

US20080212730A1 PLL/DLL dual loop data synchronization 有权
标题翻译： PLL / DLL双循环数据同步
公开(公告)号：US20080212730A1
公开(公告)日：2008-09-04
申请号：US12077002
申请日：2008-03-14
申请人： Benjamim Tang , Scott Southwell , Nicholas Steffen
发明人： Benjamim Tang , Scott Southwell , Nicholas Steffen
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H04J3/062 , H04J3/0685 , H04L7/033
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，而不是本地引用。因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

30. 发明申请

US20070257650A1 Digital Calibration with Lossless Current Sensing in a Multiphase Switched Power Converter 有权
标题翻译：数字校准与多相开关电源转换器中的无损耗电流检测
公开(公告)号：US20070257650A1
公开(公告)日：2007-11-08
申请号：US11779487
申请日：2007-07-18
申请人： Scott Southwell , Benjamim Tang , Robert Carroll , Steven Schulte
发明人： Scott Southwell , Benjamim Tang , Robert Carroll , Steven Schulte
IPC分类号： G05F1/00
CPC分类号： H02M3/1584 , H02M2001/0009
摘要： Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a known calibration current at the load and determining actual current values by the difference in measured values between when the known calibration current is applied and when it is not applied. The accurate current is determined at a known temperature and accurate temperature compensation is provided by a non-linear digital technique. Each phase of the multi-phase power regulator is individually calibrated so that balanced channels provide accurate power to the load. Also disclosed is a calibration method with minimal noise generation.
摘要翻译：公开了一种多相功率调节器，其以无损耗的方式精确地感测负载处的电流，并且基于感测的电流来调节提供给负载的功率。还公开了一种通过在负载处施加已知的校准电流来校准多相电压调节器的方法，并且通过施加已知的校准电流与不施加之间的测量值之间的差来确定实际电流值。在已知温度下确定精确电流，并通过非线性数字技术提供精确的温度补偿。单相校准多相功率调节器的每相，以便平衡通道为负载提供精确的功率。还公开了一种具有最小噪声产生的校准方法。

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