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21. 发明授权

US10778214B1 Circuit structure and power-on method thereof 有权
公开(公告)号：US10778214B1
公开(公告)日：2020-09-15
申请号：US16599356
申请日：2019-10-11
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Chien-Cheng Liu , Yun-Ru Wu , Yun-Chih Chang , Shu-Yi Kao
IPC分类号： H03K17/22
摘要： A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current.

22. 发明申请

US20150067623A1 TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM 审中-公开
标题翻译：非标准电路电路及相关机器可读介质的时序分析方法
公开(公告)号：US20150067623A1
公开(公告)日：2015-03-05
申请号：US14450279
申请日：2014-08-03
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Ying-Chieh Chen , Mei-Li Yu , Ting-Hsiung Wang , Yu-Lan Lo , Shu-Yi Kao
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register.
摘要翻译：一种应用于非标准单元电路的定时分析方法，包括：从电路识别至少第一寄存器和第二寄存器; 计算所述第一寄存器和所述第二寄存器之间的至少一个路径的至少一个路径延迟; 计算从第一时钟源到第一寄存器的第一寄存器时钟输入端的第一寄存器时钟延迟; 计算从第二时钟源到第二寄存器的第二寄存器时钟输入端的第二寄存器时钟延迟; 以及根据所述路径延迟，所述第一寄存器时钟延迟，所述第二寄存器时钟延迟以及所述第一寄存器的第一寄存器延迟确定是否针对所述第二寄存器发生定时违反。

23. 发明授权

US08726206B1 Deadlock detection method and related machine readable medium 有权
标题翻译：死锁检测方法及相关机器可读介质
公开(公告)号：US08726206B1
公开(公告)日：2014-05-13
申请号：US14051459
申请日：2013-10-11
申请人： Realtek Semiconductor Corp.
发明人： Ting-Hsiung Wang , Yu-Lan Lo , Shu-Yi Kao
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： A deadlock detection method includes: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path. A non-transitory machine readable medium stores a program code, wherein when executed by a processor, the program code enables the processor to perform the following steps: retrieving at least one power node input of a circuit design file of an integrated circuit; retrieving a starting order of the power node; retrieving a target path starting from a specific node in accordance with the starting order; and performing deadlock detection in accordance with the starting order and the target path.
摘要翻译：一种死锁检测方法包括：检索集成电路的电路设计文件的至少一个电力节点输入; 检索功率节点的起始顺序; 根据起始顺序从特定节点开始检索目标路径; 并根据起始顺序和目标路径执行死锁检测。非暂时机器可读介质存储程序代码，其中当由处理器执行时，程序代码使得处理器能够执行以下步骤：检索集成电路的电路设计文件的至少一个功率节点输入; 检索功率节点的起始顺序; 根据起始顺序从特定节点开始检索目标路径; 并根据起始顺序和目标路径执行死锁检测。

24. 发明申请

US20130298095A1 METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM 审中-公开
标题翻译：检查I / O单元连接和相关计算机可读介质的方法
公开(公告)号：US20130298095A1
公开(公告)日：2013-11-07
申请号：US13875263
申请日：2013-05-01
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Mei-Li Yu , Yu-Lan Lo , Shu-Yi Kao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result.
摘要翻译：计算机可读介质包括用于检查芯片设计的I / O单元是否具有连接错误的程序代码，其中芯片设计包括多个I / O单元和多个块，并且当程序代码由处理器执行，程序代码执行以下步骤：通过利用与I / O单元的属性相对应的检查项来检查I / O单元和块之间的连接以产生检查结果; 以及根据检查结果确定I / O单元是否具有连接错误。

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