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21. 发明授权

US08171328B2 State history storage for synchronizing redundant processors 有权
标题翻译：用于同步冗余处理器的状态历史存储
公开(公告)号：US08171328B2
公开(公告)日：2012-05-01
申请号：US12347961
申请日：2008-12-31
申请人： Shubhendu S. Mukherjee , Arijit Biswas , Paul B. Racunas , Steven E. Raasch
发明人： Shubhendu S. Mukherjee , Arijit Biswas , Paul B. Racunas , Steven E. Raasch
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , G06F11/1407 , G06F11/1641 , G06F11/1658 , G06F11/1683 , G06F11/1691
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
摘要翻译：公开了使用状态历史同步冗余处理器的发明的实施例。在一个实施例中，装置包括两个处理器，每个处理器的状态存储器和控制逻辑。每个处理器都要执行相同的指令。状态存储器是存储由处理器执行的每个指令的压缩处理器状态信息。控制逻辑是基于来自状态存储器的条目来同步两个处理器。

22. 发明申请

US20140122811A1 Method And Apparatus For Error Correction In A Cache 有权
标题翻译：缓存中误差校正的方法和装置
公开(公告)号：US20140122811A1
公开(公告)日：2014-05-01
申请号：US13664682
申请日：2012-10-31
申请人： Stanislav Shwartsman , Raanan Sade , Larisa Novakovsky , Arijit Biswas
发明人： Stanislav Shwartsman , Raanan Sade , Larisa Novakovsky , Arijit Biswas
IPC分类号： G06F12/08
CPC分类号： G06F12/121 , G06F11/1064 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F2212/1032 , G06T1/20
摘要： A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed.
摘要翻译：处理器包括执行指令的核心和耦合到核心并且具有多个条目的高速缓存存储器。高速缓冲存储器的每个条目可以包括包括多个数据存储部分的数据存储部分，每个数据存储部分存储对应的数据部分。每个条目还可以包括用于存储多个部分修改指示符的元数据存储器，每个部分修改指示符对应于数据存储部分之一。每个部分修改指示符用于指示存储在相应的数据存储部分中的数据部分是否已被修改，而与条目的高速缓存一致性状态信息无关。其他实施例被描述为所要求保护的。

23. 发明申请

US20100169582A1 Obtaining data for redundant multithreading (RMT) execution 有权
标题翻译：获取冗余多线程（RMT）执行的数据
公开(公告)号：US20100169582A1
公开(公告)日：2010-07-01
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08 , G06F12/00 , G06F9/46
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。描述和要求保护其他实施例。

24. 发明申请

US20100158916A1 DIAGNOSTIC BIOMOLECULE(S) 有权
标题翻译：诊断生物分子（S）
公开(公告)号：US20100158916A1
公开(公告)日：2010-06-24
申请号：US12440004
申请日：2007-08-20
申请人： Mahesh Arjandas Choolani , Khalil Razvi B M Jabarullah Khan , Loganath Annamalai , Arijit Biswas , Changqing Zhao
发明人： Mahesh Arjandas Choolani , Khalil Razvi B M Jabarullah Khan , Loganath Annamalai , Arijit Biswas , Changqing Zhao
IPC分类号： A61K39/395 , G01N33/53 , A61K31/7088
CPC分类号： G01N33/574 , G01N33/57449 , G01N2800/52
摘要： The present invention relates to methods for the identification and/or quantification of biomolecule(s). There is also provided a novel method of identifying and/or quantitating biomolecule(s) in a proliferative cell disorder by providing at least one cyst fluid sample and determining the expression of haptoglobin protein, derivative, mutant and/or fragment thereof.
摘要翻译：本发明涉及用于鉴定和/或定量生物分子的方法。还提供了通过提供至少一种囊状液样品并确定触珠蛋白蛋白，其衍生物，突变体和/或片段的表达来鉴定和/或定量增殖性细胞病症中的生物分子的新方法。

25. 发明申请

US20090281798A1 PREDICTIVE ENCODING OF A MULTI CHANNEL SIGNAL 审中-公开
标题翻译：多通道信号的预测编码
公开(公告)号：US20090281798A1
公开(公告)日：2009-11-12
申请号：US11915004
申请日：2006-05-09
申请人： Albertus Cornelis Den Brinker , Arijit Biswas
发明人： Albertus Cornelis Den Brinker , Arijit Biswas
IPC分类号： G10L19/04
CPC分类号： G10L19/008 , G10L19/06
摘要： A multi channel encoder (100) comprises a multi channel linear predictive analyzer (105) for linear predictive coding of a multi channel signal. A prediction controller (101) comprises a prediction parameter generator (301) which generates linear prediction coding parameter matrices for the multi channel signal which are then mapped to reflection matrices. The reflection matrices may specifically be normalized backward or forward reflection matrices. The reflection matrices are encoded by a reflection parameter encoder (305) and combined with other encoded data in a multiplexer (109) to generate encoded data for the multi channel signal. The reflection parameter encoder (305) may specifically decompose the reflection matrices using an Eigenvalue decomposition or a singular value decomposition and the resulting data may be quantized for transmission. A decoder (200) receives the encoded data and obtains the prediction parameters by performing the inverse operation.
摘要翻译：多通道编码器（100）包括用于多通道信号的线性预测编码的多通道线性预测分析器（105）。预测控制器（101）包括预测参数生成器（301），该预测参数生成器生成多信道信号的线性预测编码参数矩阵，然后映射到反射矩阵。反射矩阵可以具体地是归一化的反向或正向反射矩阵。反射矩阵由反射参数编码器（305）编码并与多路复用器（109）中的其它编码数据组合以产生用于多通道信号的编码数据。反射参数编码器（305）可以使用特征值分解或奇异值分解来具体地分解反射矩阵，并且可以量化所得到的数据以进行传输。解码器（200）接收编码数据并通过执行逆运算来获得预测参数。

26. 发明授权

US07475321B2 Detecting errors in directory entries 有权
标题翻译：检测目录条目中的错误
公开(公告)号：US07475321B2
公开(公告)日：2009-01-06
申请号：US11027391
申请日：2004-12-29
申请人： Sudhanva Gurumurthi , Arijit Biswas , Joel S. Emer , Shubhendu S. Mukherjee
发明人： Sudhanva Gurumurthi , Arijit Biswas , Joel S. Emer , Shubhendu S. Mukherjee
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/0793 , G06F11/0724 , G06F12/0817 , G06F2212/1032 , Y10S707/99933 , Y10S707/99934
摘要： In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured to detect an error in an entry of the directory based on a coherency protocol and a state of a status indicator and presence vector of the entry, and without the storage of error correction or parity information in the entry. In some embodiments, the node may correct the error using state information obtained from other nodes.
摘要翻译：在一个实施例中，本发明包括一种系统，其可以是具有多个节点的多处理器系统，每个具有处理器和高速缓存。系统可以包括存储在包括具有一致性信息的条目的存储器中的目录。节点中的至少一个可以被配置为基于一致性协议和条目的状态指示符和存在向量的状态来检测目录的条目中的错误，并且在不存在错误校正或奇偶校验信息的存储中条目。在一些实施例中，节点可以使用从其他节点获得的状态信息来校正错误。

27. 发明申请

US20180262407A1 Telemetry Architecture for Integrated Circuits and Cloud Infrastructure 审中-公开
公开(公告)号：US20180262407A1
公开(公告)日：2018-09-13
申请号：US15914764
申请日：2018-03-07
申请人： Arijit Biswas , Johan G. Van De Groenendaal , Jeremy J. Shrall , Jeremiah D. Williamson , Rahul Khanna , Robert F. Kwasnick , Arthur E. Handras , Victor T. Lau
发明人： Arijit Biswas , Johan G. Van De Groenendaal , Jeremy J. Shrall , Jeremiah D. Williamson , Rahul Khanna , Robert F. Kwasnick , Arthur E. Handras , Victor T. Lau
IPC分类号： H04L12/26
CPC分类号： H04L43/04 , G06F9/44 , H04L43/062 , H04L43/065 , H04L43/0876 , H04L43/12 , H04L67/12
摘要： Examples include systems and methods for implementing telemetry architecture on an integrated circuit are disclosed. In accordance with one embodiment, telemetric architecture on an integrated circuit may include a telemetric semantic space (TSS) such that the TSS is a memory space that stores a set of telemetric data from a plurality of sensors coupled to the integrated circuit. The telemetry architecture may also include a telemetry aggregator that aggregates the set of telemetric data from the plurality of sensors. Furthermore, the telemetry architecture may include a telemetry consumer that queries the telemetry aggregator for a subset of the set of telemetric data stored in the TSS.

28. 发明授权

US09317561B2 Scene change detection around a set of seed points in media data 有权
标题翻译：媒体数据中一组种子点周围的场景变化检测
公开(公告)号：US09317561B2
公开(公告)日：2016-04-19
申请号：US13997860
申请日：2011-12-15
申请人： Barbara Resch , Regunathan Radhakrishnan , Arijit Biswas , Jonas Engdegard
发明人： Barbara Resch , Regunathan Radhakrishnan , Arijit Biswas , Jonas Engdegard
IPC分类号： G06F17/00 , G06F17/30 , G10H1/00 , H04R29/00 , G10L25/48
CPC分类号： H04R29/00 , G06F17/00 , G06F17/3053 , G10H1/0008 , G10H2210/061 , G10H2240/151 , G10L25/48
摘要： Techniques for scene change detection around seed points in media data are provided. Media features of many different types may be extracted from the media data. One or more statistical patterns of media features in a plurality of time-wise intervals around a plurality of seed time points of the media data may be determined using one or more types of features extractable from the media data. At least one of the one or more types of features comprises a type of features that captures structural properties, tonality including harmony and melody, timbre, rhythm, loudness, stereo mix, or a quantity of sound sources as related to the media data. A plurality of beginning scene change points and a plurality of ending scene change points in the media data may be detected, based on the one or more statistical patterns, for the plurality of seed time points in the media data.
摘要翻译：提供媒体数据中种子点周围场景变化检测技术。可以从媒体数据中提取许多不同类型的媒体特征。可以使用从媒体数据可提取的一种或多种类型的特征来确定围绕媒体数据的多个种子时间点的多个时间间隔中的媒体特征的一个或多个统计模式。一种或多种类型的特征中的至少一种包括捕获与媒体数据相关的结构性质，包括和声和旋律的音调，音色，节奏，响度，立体声混合或数量的声源的特征的类型。可以基于媒体数据中的多个种子时间点的一个或多个统计模式来检测媒体数据中的多个起始场景变化点和多个结束场景变化点。

29. 发明授权

US08914672B2 General purpose hardware to replace faulty core components that may also provide additional processor functionality 有权
标题翻译：通用硬件替代可能还提供额外处理器功能的故障核心组件
公开(公告)号：US08914672B2
公开(公告)日：2014-12-16
申请号：US12647940
申请日：2009-12-28
申请人： Steven E. Raasch , Michael D. Powell , Shubhendu S. Mukherjee , Arijit Biswas
发明人： Steven E. Raasch , Michael D. Powell , Shubhendu S. Mukherjee , Arijit Biswas
IPC分类号： G06F11/00 , G06F9/38 , G06F11/20 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/30196 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F11/2028 , G06F11/2038 , G06F11/2043
摘要： An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
摘要翻译：本文描述了用于替换故障核心部件的装置和方法。提供通用硬件来代替核心管道组件，如执行单元。在执行单元替换的实施例中，提供代理单元，使得映射逻辑能够将与故障执行单元相对应的指令/操作映射到代理单元。因此，代理单元能够接收操作，将其发送到通用硬件执行，然后将执行结果写回寄存器文件; 它基本上取代了有缺陷的执行单元，允许出售有缺陷单元的处理器或继续操作。

30. 发明申请

US20140189252A1 DYNAMIC CACHE WRITE POLICY 有权
标题翻译：动态缓存写策略
公开(公告)号：US20140189252A1
公开(公告)日：2014-07-03
申请号：US13732301
申请日：2012-12-31
申请人： Arijit Biswas
发明人： Arijit Biswas
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F12/0804 , G06F12/0811 , G06F12/0815 , G06F2212/1032
摘要： A system, processor and method to monitor specific cache events and behavior based on established principles of quantized architectural vulnerability factor (AVF) through the use of a dynamic cache write policy controller. The output of the controller is then used to set the write back or write through mode policy for any given cache. This method can be used to change cache modes dynamically and does not require the system to be rebooted. The dynamic nature of the controller provides the capability of intelligently switching from reliability to performance mode and back as needed. This method eliminates the residency time of dirty lines in a cache, which increases soft errors (SER) resiliency of protected caches in the system and reduces detectable unrecoverable errors (DUE), while keeping implementation cost of hardware at a minimum.
摘要翻译：通过使用动态缓存写策略控制器，基于量化架构漏洞因子（AVF）的已建立原则来监视特定缓存事件和行为的系统，处理器和方法。然后，控制器的输出用于设置任何给定缓存的回写或写模式策略。此方法可用于动态更改缓存模式，不需要重新启动系统。控制器的动态特性提供了从可靠性到性能模式智能切换的能力，并根据需要返回。该方法消除了缓存中脏线的驻留时间，这增加了系统中受保护高速缓存的软错误（SER）弹性，并降低了可检测的不可恢复错误（DUE），同时将硬件的实施成本降到最低。

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