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21. 发明授权

US07853755B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US07853755B1
公开(公告)日：2010-12-14
申请号：US11754162
申请日：2007-05-25
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
摘要翻译：多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

22. 发明授权

US07853752B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US07853752B1
公开(公告)日：2010-12-14
申请号：US11754016
申请日：2007-05-25
申请人： Anant Agarwal , Matthew Mattina
发明人： Anant Agarwal , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor includes a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more input/output modules configured to couple data between an input/output interface and at least one of a memory interface and a cache memory. Each of at least some of the cache memories is assigned as a home location for caching a corresponding portion of the main memory, and is configured to maintain the cache memory based on whether a processor core or an input/output module is requesting access to the cache memory.
摘要翻译：多核处理器包括多个高速缓存存储器; 多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联; 一个或多个存储器接口，提供从高速缓冲存储器到主存储器的存储器访问路径; 以及被配置为在输入/输出接口与存储器接口和高速缓冲存储器中的至少一个之间耦合数据的一个或多个输入/输出模块。至少一些高速缓冲存储器中的每一个被分配为用于缓存主存储器的对应部分的归属位置，并且被配置为基于处理器核心或输入/输出模块是否要求访问主存储器来维护高速缓冲存储器高速缓存存储器。

23. 发明授权

US07774553B1 Caching in multicore and multiprocessor architectures 有权
公开(公告)号：US07774553B1
公开(公告)日：2010-08-10
申请号：US11754118
申请日：2007-05-25
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
摘要： A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.

24. 发明授权

US08065259B1 Pattern matching in a multiprocessor environment 有权
标题翻译：多处理器环境中的模式匹配
公开(公告)号：US08065259B1
公开(公告)日：2011-11-22
申请号：US12890996
申请日：2010-09-27
申请人： Kenneth M. Steele , Anant Agarwal
发明人： Kenneth M. Steele , Anant Agarwal
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/30982 , G06F21/564 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.
摘要翻译：多个互连处理引擎中的模式匹配包括：通过接口接收输入序列流并存储输入序列; 存储用于将输入序列与用于由第一组一个或多个处理引擎访问的存储器中的一个或多个模式进行匹配的指令，以及存储用于将输入序列匹配到存储器中的一个或多个模式的指令，所述存储器可由第二组一个或多个处理发动机; 将识别所选输入序列的信息分发到所述第一和第二组处理引擎; 以及检索所识别的输入序列以在所述第一和第二组处理引擎中执行模式匹配。

25. 发明授权

US07805392B1 Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table 有权
标题翻译：基于状态转换表中的向量顺序，在具有有限状态自动机转换的多处理器环境中的模式匹配
公开(公告)号：US07805392B1
公开(公告)日：2010-09-28
申请号：US11564694
申请日：2006-11-29
申请人： Kenneth M. Steele , Anant Agarwal
发明人： Kenneth M. Steele , Anant Agarwal
IPC分类号： G06N5/02
CPC分类号： G06F17/30982 , G06F21/564 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.
摘要翻译：多个互连处理引擎中的模式匹配包括：通过接口接收输入序列流并存储输入序列; 存储用于将输入序列与用于由第一组一个或多个处理引擎访问的存储器中的一个或多个模式进行匹配的指令，以及存储用于将输入序列匹配到存储器中的一个或多个模式的指令，所述指令可由第二组一个或多个处理发动机; 将识别所选输入序列的信息分发到所述第一和第二组处理引擎; 以及检索所识别的输入序列以在所述第一和第二组处理引擎中执行模式匹配。

26. 发明授权

US07818725B1 Mapping communication in a parallel processing environment 有权
标题翻译：在并行处理环境中映射通信
公开(公告)号：US07818725B1
公开(公告)日：2010-10-19
申请号：US11414473
申请日：2006-04-28
申请人： Anant Agarwal , Patrick Robert Griffin
发明人： Anant Agarwal , Patrick Robert Griffin
IPC分类号： G06F9/45
CPC分类号： G06F15/17318
摘要： An the integrated circuit comprises a plurality of processor cores interconnected by an interconnection network. A method for generating instructions to be executed in the integrated circuit comprises accepting a plurality of programs, at least some of the programs including one or more communication operations to communicate with other programs; mapping each program to one or more of the processor cores; determining correspondence among communication operations in the programs; and mapping communication for corresponding communication operations to resources associated with the interconnection network.
摘要翻译：集成电路包括通过互连网络互连的多个处理器核心。一种用于产生要在集成电路中执行的指令的方法，包括接受多个节目，所述节目中的至少一些包括一个或多个通信操作以与其他节目通信; 将每个程序映射到一个或多个处理器核心; 确定程序中的通信操作之间的对应关系; 并将用于相应通信操作的通信映射到与互连网络相关联的资源。

27. 发明授权

US09009660B1 Programming in a multiprocessor environment 有权
标题翻译：在多处理器环境中编程
公开(公告)号：US09009660B1
公开(公告)日：2015-04-14
申请号：US11564723
申请日：2006-11-29
申请人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
发明人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
IPC分类号： G06F9/44 , G06F9/45 , G06F9/48
CPC分类号： G06F8/445 , G06F8/30 , G06F8/314 , G06F8/41 , G06F8/427 , G06F8/437 , G06F8/447 , G06F8/451 , G06F8/453 , G06F9/48 , G06F9/546 , G06F2209/548
摘要： Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.
摘要翻译：在多处理器环境中的编程包括接受定义多个处理模块的程序规范和用于在模块的端口之间发送数据的一个或多个通道，将每个处理模块映射到一组一个或多个处理引擎上互联处理引擎的网络，以及至少一些信道，将网络中的一个或多个处理引擎的一个或多个元素分配给用于在各个处理模块之间发送数据的信道。

28. 发明授权

US08086554B1 Pattern matching in a multiprocessor environment 有权
公开(公告)号：US08086554B1
公开(公告)日：2011-12-27
申请号：US13188580
申请日：2011-07-22
申请人： Kenneth M. Steele , Anant Agarwal
发明人： Kenneth M. Steele , Anant Agarwal
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/30982 , G06F21/564 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.

29. 发明授权

US08250556B1 Distributing parallelism for parallel processing architectures 有权
标题翻译：分布并行处理架构
公开(公告)号：US08250556B1
公开(公告)日：2012-08-21
申请号：US12028003
申请日：2008-02-07
申请人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
发明人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/41 , G06F8/445 , G06F12/0837
摘要： A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.
摘要翻译：一种系统包括由互连网互连的多个计算单元。一种用于配置系统的方法包括：将指令的初始划分接收到对应于节目的不同部分的初始子集; 将所述指令的精细分割形成为精简子集，所述精化子集包括所述初始子集中的一个或多个，包括根据所述第一子集和第一子集之间的通信成本的比较来确定是否组合第一子集和第二子集以形成第三子集所述第二子集和所述第三子集的负载成本至少部分地基于每个周期由计算单元发出的指令的数量; 以及将每个经精炼的指令子集分配给所述计算单元之一用于在所分配的计算单元上执行。

30. 发明授权

US06804814B1 Method for simulating back program execution from a traceback sequence 失效
标题翻译：从回溯序列模拟程序执行的方法
公开(公告)号：US06804814B1
公开(公告)日：2004-10-12
申请号：US09474680
申请日：1999-12-29
申请人： Andrew E. Ayers , Richard Schooler , Anant Agarwal
发明人： Andrew E. Ayers , Richard Schooler , Anant Agarwal
IPC分类号： G06F944
CPC分类号： G06F11/3636 , G06F11/3624 , G06F11/3644
摘要： A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace. In one embodiment, the instruction trace is displayed and a value set is determined for an instruction upon a request by the user indicating the instruction for which the value set is desired.
摘要翻译：程序执行数据跟踪是通过在程序执行过程中记录数值集和指令跟踪进行测量而创建的。通过根据指令轨迹从与从设定到第二指令的记录值相关联的第一指令向后或向前模拟指令，为第二指令确定值集合。后向和前向模拟可以相互补充。为了进行反向仿真，优选地保持模拟指令表，其将在指令轨迹中遇到的程序指令与反转相关程序指令的操作的模拟指令相关联。优选地，将一个或多个探针插入到程序中以保存其值可能难以确定的特定变量的值。优选地，指示轨迹显示在数据轨迹旁边并与之相关联。在一个实施例中，显示指令轨迹，并且在用户请求时指示针对期望值设置的指令的指令确定值集合。

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