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21. 发明申请

US20070218665A1 Cross-point memory array 审中-公开
标题翻译：交叉点存储器阵列
公开(公告)号：US20070218665A1
公开(公告)日：2007-09-20
申请号：US11637967
申请日：2006-12-13
申请人： Pantas Sutardja , Albert Wu
发明人： Pantas Sutardja , Albert Wu
IPC分类号： H01L21/28
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells. Each of the PCM cells includes diode arranged adjacent to a metallization layer; a heater element arranged adjacent to the diode, and a phase-change material arranged adjacent to the heater element.
摘要翻译：相变存储器（PCM）系统包括包括多个PCM单元的PCM单元阵列。每个PCM单元包括邻近金属化层布置的二极管; 与二极管相邻布置的加热器元件，以及邻近加热器元件设置的相变材料。

22. 发明授权

US07622731B2 Cross-point memory array 有权
标题翻译：交叉点存储器阵列
公开(公告)号：US07622731B2
公开(公告)日：2009-11-24
申请号：US11709631
申请日：2007-02-22
申请人： Pantas Sutardja , Albert Wu
发明人： Pantas Sutardja , Albert Wu
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A circuit comprises a bulk silicon integrated circuit (IC). A first metallization layer is arranged adjacent to said bulk silicon IC. Phase change memory (PCM) is arranged adjacent to said first metallization layer and comprises a plurality of PCM cells each including a phase-change material, a heater that selectively heats said phase-change material, and a diode in series with said phase-change material.
摘要翻译：电路包括体硅集成电路（IC）。第一金属化层被布置成与所述体硅IC相邻。相变存储器（PCM）被布置为与所述第一金属化层相邻并且包括多个PCM单元，每个PCM单元包括相变材料，选择性地加热所述相变材料的加热器和与所述相变量串联的二极管材料。

23. 发明授权

US08501619B1 Methods for forming a plurality of contact holes in a microelectronic device 有权
标题翻译：在微电子器件中形成多个接触孔的方法
公开(公告)号：US08501619B1
公开(公告)日：2013-08-06
申请号：US13212065
申请日：2011-08-17
申请人： Albert Wu , Chien-Chuan Wei
发明人： Albert Wu , Chien-Chuan Wei
IPC分类号： H01L21/47
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.
摘要翻译：一种方法，包括：在微电子器件的衬底上形成介电层; 在所述电介质层上形成光致抗蚀剂层; 执行光致抗蚀剂层的第一曝光以允许在第一多个位置处去除介电层的部分; 在执行第一曝光之后，进行光致抗蚀剂层的第二次曝光以允许介电层的部分在与第一多个位置不同的第二多个位置处被去除; 在i）所述第一多个位置和ii）所述第二多个位置中的每一个处去除所述介电层的所述部分; 以及在i）所述第一多个位置和ii）所述第二多个位置中蚀刻所述电介质层，以及分别在所述第一多个位置中的每一个处分别形成接触孔，以及ii）所述第二多个位置。

24. 发明授权

US08368214B2 Alpha shielding techniques and configurations 有权
标题翻译： Alpha屏蔽技术和配置
公开(公告)号：US08368214B2
公开(公告)日：2013-02-05
申请号：US12628059
申请日：2009-11-30
申请人： Nelson Tam , Albert Wu , Chien-Chuan Wei
发明人： Nelson Tam , Albert Wu , Chien-Chuan Wei
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/56 , H01L21/563 , H01L23/556 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05073 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2224/73203 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/05552 , H01L2924/00
摘要： Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种包括具有多个集成电路器件的半导体管芯的器件，通过互连层电耦合到多个集成电路器件中的至少一个集成电路器件的焊盘结构，设置在多个集成电路器件上的电绝缘层所述互连层，设置在所述电绝缘层中并电耦合到所述焊盘结构的第一屏蔽结构，电耦合到所述第一屏蔽结构的球下金属化（UBM）结构以及电耦合到所述UBM结构的焊料凸块，所述焊料凸块包括能够发射α粒子的焊料凸块材料，其中所述第一屏蔽结构位于所述焊料凸块和所述多个集成电路器件之间，以将所述多个集成电路器件与所述α粒子进行屏蔽。可以描述和/或要求保护其他实施例。

25. 发明授权

US08003523B1 Methods for forming a plurality of contact holes in a microelectric device 有权
标题翻译：在微电子装置中形成多个接触孔的方法
公开(公告)号：US08003523B1
公开(公告)日：2011-08-23
申请号：US12767626
申请日：2010-04-26
申请人： Albert Wu , Chien-Chuan Wei
发明人： Albert Wu , Chien-Chuan Wei
IPC分类号： H01L21/475
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.
摘要翻译：一种方法，包括：在微电子器件的衬底上形成介电层; 在所述电介质层上形成光致抗蚀剂层; 执行光致抗蚀剂层的第一曝光以允许在第一多个位置处去除介电层的部分; 在执行第一曝光之后，进行光致抗蚀剂层的第二次曝光以允许介电层的部分在与第一多个位置不同的第二多个位置处被去除; 在i）所述第一多个位置和ii）所述第二多个位置中的每一个处去除所述介电层的所述部分; 以及在i）所述第一多个位置和ii）所述第二多个位置中蚀刻所述电介质层，以及分别在所述第一多个位置中的每一个处分别形成接触孔，以及ii）所述第二多个位置。

26. 发明授权

US07834341B2 Phase change material (PCM) memory devices with bipolar junction transistors and methods for making thereof 有权
标题翻译：具有双极结型晶体管的相变材料（PCM）存储器件及其制造方法
公开(公告)号：US07834341B2
公开(公告)日：2010-11-16
申请号：US12024986
申请日：2008-02-01
申请人： Albert Wu , Chien-Chuan Wei
发明人： Albert Wu , Chien-Chuan Wei
IPC分类号： H01L21/00 , H01L29/04 , G11C5/06
CPC分类号： H01L45/144 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite of the substrate. A heating element may then be constructed on the emitter of the BJT structure, wherein the heating element includes a material to generate heat when provided with an electrical current from the emitter. A phase change material (PCM) cell may then be built on the heating element opposite of the BJT structure.
摘要翻译：本文描述了用于制造高度紧凑的PCM存储器件的方法。所述方法可以包括在衬底上形成双极结型晶体管（BJT）结构，包括在衬底上形成BJT结构的基底，并在与衬底相对的基底的顶部上形成BJT结构的发射极。然后可以在BJT结构的发射器上构造加热元件，其中，当提供来自发射器的电流时，加热元件包括产生热量的材料。然后可以在与BJT结构相对的加热元件上建立相变材料（PCM）单元。

27. 发明申请

US20110175218A1 PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：具有半导体基板的封装组件
公开(公告)号：US20110175218A1
公开(公告)日：2011-07-21
申请号：US12973249
申请日：2010-12-20
申请人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
发明人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上，半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。可以描述和/或要求保护其他实施例。

28. 发明授权

US07704875B1 High-density contact holes 有权
标题翻译：高密度接触孔
公开(公告)号：US07704875B1
公开(公告)日：2010-04-27
申请号：US12024784
申请日：2008-02-01
申请人： Albert Wu , Chien-Chuan Wei
发明人： Albert Wu , Chien-Chuan Wei
IPC分类号： H01L21/475
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： Methods for patterning high-density contact holes and contacts are described herein. Embodiments of the present invention provide a method comprising depositing a first dummy layer over a substrate to form a first pattern; depositing a second dummy layer over the substrate to form a second pattern, the second pattern overlapping the first pattern at a plurality of locations; etching the first and second dummy layers to form a plurality of posts at the plurality of locations; forming a dielectric layer over the substrate; and etching the posts to form a plurality of contact holes in the dielectric layer. Other embodiments may be described and claimed.
摘要翻译：本文描述了用于图案化高密度接触孔和触点的方法。本发明的实施例提供了一种方法，包括在衬底上沉积第一虚拟层以形成第一图案; 在所述衬底上沉积第二虚拟层以形成第二图案，所述第二图案在所述多个位置处与所述第一图案重叠; 蚀刻第一和第二虚拟层以在多个位置形成多个柱; 在所述衬底上形成介电层; 并且蚀刻所述柱以在所述介电层中形成多个接触孔。可以描述和要求保护其他实施例。

29. 发明申请

US20100140760A1 ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS 有权
标题翻译： ALPHA屏蔽技术和配置
公开(公告)号：US20100140760A1
公开(公告)日：2010-06-10
申请号：US12628059
申请日：2009-11-30
申请人： Nelson Tam , Albert Wu , Chien-Chuan Wei
发明人： Nelson Tam , Albert Wu , Chien-Chuan Wei
IPC分类号： H01L23/556 , H01L21/56
CPC分类号： H01L21/56 , H01L21/563 , H01L23/556 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05073 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2224/73203 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/05552 , H01L2924/00
摘要： Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种包括具有多个集成电路器件的半导体管芯的器件，通过互连层电耦合到多个集成电路器件中的至少一个集成电路器件的焊盘结构，设置在多个集成电路器件上的电绝缘层所述互连层，设置在所述电绝缘层中并电耦合到所述焊盘结构的第一屏蔽结构，电耦合到所述第一屏蔽结构的球下金属化（UBM）结构以及电耦合到所述UBM结构的焊料凸块，所述焊料凸块包括能够发射α粒子的焊料凸块材料，其中所述第一屏蔽结构位于所述焊料凸块和所述多个集成电路器件之间，以将所述多个集成电路器件与所述α粒子进行屏蔽。可以描述和/或要求保护其他实施例。

30. 发明申请

US20080185570A1 PHASE CHANGE MATERIAL (PCM) MEMORY DEVICES WITH BIPOLAR JUNCTION TRANSISTORS AND METHODS FOR MAKING THEREOF 有权
标题翻译：具有双极性晶体管的相变材料（PCM）存储器件及其制造方法
公开(公告)号：US20080185570A1
公开(公告)日：2008-08-07
申请号：US12024986
申请日：2008-02-01
申请人： Albert Wu , Chien-Chuan Wei
发明人： Albert Wu , Chien-Chuan Wei
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite of the substrate. A heating element may then be constructed on the emitter of the BJT structure, wherein the heating element includes a material to generate heat when provided with an electrical current from the emitter. A phase change material (PCM) cell may then be built on the heating element opposite of the BJT structure.
摘要翻译：本文描述了用于制造高度紧凑的PCM存储器件的方法。所述方法可以包括在衬底上形成双极结型晶体管（BJT）结构，包括在衬底上形成BJT结构的基底，并在与衬底相对的基底的顶部上形成BJT结构的发射极。然后可以在BJT结构的发射器上构造加热元件，其中，当提供来自发射器的电流时，加热元件包括产生热量的材料。然后可以在与BJT结构相对的加热元件上建立相变材料（PCM）单元。

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