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21. 发明申请

US20130045569A1 METHOD AND APPARATUS FOR FABRICATING INTEGRATED CIRCUIT DEVICE USING SELF-ORGANIZING FUNCTION 有权
标题翻译：使用自组织功能制作集成电路设备的方法和装置
公开(公告)号：US20130045569A1
公开(公告)日：2013-02-21
申请号：US13589590
申请日：2012-08-20
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/50
CPC分类号： H01L21/6835 , H01L21/568 , H01L21/6836 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68313 , H01L2221/68327 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13147 , H01L2224/13184 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73259 , H01L2224/75 , H01L2224/7598 , H01L2224/78743 , H01L2224/81097 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/81907 , H01L2224/83193 , H01L2224/838 , H01L2224/83907 , H01L2224/95001 , H01L2224/95145 , H01L2224/95146 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12043 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01031
摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of sticky material. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.
摘要翻译：在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。半导体芯片13的临时粘合部分12b通过粘性材料临时粘附到载体基板73a的相应临时粘合区域72a。然后将载体基板73a压向支撑基板或期望的电路层，从而使载体基板73a上的芯片13的连接部分12与支撑基板或电路层上的相应的预定位置接触。此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。

22. 发明授权

US08229539B1 Brain probe and method for manufacturing same 有权
标题翻译：脑探针及其制造方法
公开(公告)号：US08229539B1
公开(公告)日：2012-07-24
申请号：US13207715
申请日：2011-08-11
申请人： Makoto Motoyoshi , Mitsumasa Koyanagi , Hajime Mushiake , Tetsu Tanaka , Norihiro Katayama
发明人： Makoto Motoyoshi , Mitsumasa Koyanagi , Hajime Mushiake , Tetsu Tanaka , Norihiro Katayama
IPC分类号： A61B5/0478 , A61B1/05 , H01R43/00
CPC分类号： H01R11/18 , A61B5/04001 , A61B5/0478 , A61B2562/046 , A61B2562/125 , A61N1/0534 , H01R2201/12 , Y10T29/49117
摘要： A brain probe includes: a core probe made from a metal; and n electrode plates attached so as to cover an entire side surface circumference of the core probe and forming n side planes providing an n-angular cross section (n is an integer equal to or greater than 3). Each of the electrode plates is manufactured by a LSI manufacturing process, and provided with at least one electrode and a lead-out wiring extending in a longitudinal direction of a side plane from each of the at least one electrode.
摘要翻译：脑探针包括：由金属制成的芯探针; 和n个电极板，以覆盖芯探针的整个侧表面圆周并形成提供n角横截面（n为等于或大于3的整数）的n个侧面。每个电极板通过LSI制造工艺制造，并且设置有至少一个电极和从每个至少一个电极的侧面的纵向方向延伸的引出布线。

23. 发明授权

US07906363B2 Method of fabricating semiconductor device having three-dimensional stacked structure 有权
标题翻译：制造具有三维堆叠结构的半导体器件的方法
公开(公告)号：US07906363B2
公开(公告)日：2011-03-15
申请号：US11573976
申请日：2005-08-19
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/563 , H01L21/6836 , H01L21/8221 , H01L23/481 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0629 , H01L27/0688 , H01L27/14636 , H01L2221/68359 , H01L2224/0401 , H01L2224/0557 , H01L2224/11002 , H01L2224/114 , H01L2224/1146 , H01L2224/1147 , H01L2224/1162 , H01L2224/13025 , H01L2224/16146 , H01L2224/17181 , H01L2224/73204 , H01L2224/81193 , H01L2224/81801 , H01L2224/83104 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/10253 , H01L2924/12043 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/11 , H01L2224/05552 , H01L2224/80001
摘要： A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
摘要翻译：一种通过在支撑基板上层叠半导体电路层而制造具有三维层叠结构的半导体器件的方法，包括以下步骤：在半导体衬底中形成沟槽; 用导电材料填充沟槽内部以形成导电插塞; 在形成有导电塞的半导体基板的内部或表面上形成元件或电路; 用第二绝缘膜覆盖形成元件或电路的半导体衬底的表面; 并且通过布线结构将所述第二绝缘膜与所述支撑基板或所述半导体电路层中的剩余的一个接合，将所述半导体基板固定到所述支撑基板或所述半导体电路层中的剩余的一个; 选择性地去除所述半导体衬底以暴露所述第一绝缘膜; 并选择性地去除第一绝缘膜。

24. 发明申请

US20090023243A1 METHOD AND APPARATUS FOR FABRICATING INTEGRATED CIRCUIT DEVICE USING SELF-ORGANIZING FUNCTION 有权
标题翻译：使用自组织功能制作集成电路设备的方法和装置
公开(公告)号：US20090023243A1
公开(公告)日：2009-01-22
申请号：US11813032
申请日：2005-12-28
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/50 , H01L21/67
CPC分类号： H01L21/6835 , H01L21/568 , H01L21/6836 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68313 , H01L2221/68327 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13147 , H01L2224/13184 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73259 , H01L2224/75 , H01L2224/7598 , H01L2224/78743 , H01L2224/81097 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/81907 , H01L2224/83193 , H01L2224/838 , H01L2224/83907 , H01L2224/95001 , H01L2224/95145 , H01L2224/95146 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12043 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01031
摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.
摘要翻译：在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。半导体芯片13的临时粘合部分12b通过水膜81临时粘附到载体基板73a的相应的临时粘合区域72a上。然后将载体基板73a压向支撑基板或所需的电路层，从而接触连接部分载体基板73a上的芯片13的12个，在支撑基板或电路层上具有对应的预定位置。此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。

25. 发明申请

US20080171411A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT EXCELLENT IN CHARGE RETENTION PROPERTIES AND PROCESS FOR PRODUCING THE SAME 有权
标题翻译：非挥发性半导体存储元件在充电保持性方面的优异性及其制造方法
公开(公告)号：US20080171411A1
公开(公告)日：2008-07-17
申请号：US12046763
申请日：2008-03-12
申请人： Masaaki TAKATA , Mitsumasa Koyanagi
发明人： Masaaki TAKATA , Mitsumasa Koyanagi
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28273 , H01L21/3105 , H01L21/316 , H01L21/31645 , H01L29/42332 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory element enabling to improve insulation performance of an insulator around a floating gate and to decrease the ratio of oxidized metal ultrafine particles in the floating gate, are provided.In a process for producing nonvolatile semiconductor memory element comprising a floating gate made of a hardly oxidizable material having a Gibbs' formation free energy for forming its oxide higher than that of Si in a range of from 0° C. to 1,200° C., and an insulator made of an oxide of an easily oxidizable material surrounding the floating gate and having such an energy equivalent or lower than that of Si, the floating gate made of hardly oxidizable material is formed by using a physical forming method, the oxide of the easily oxidizable material is formed by using a physical forming method or a chemical forming method, and after a gate insulation film is formed, a heat treatment is carried out in a mixed atmosphere of an oxidizing gas and a reducing gas in a temperature range of from 0° C. to 1,200° C. while the mixture ratio of the mixed gas and the temperature are controlled so that only the hardly oxidizable material is reduced and only the oxide of the easily oxidizable material is oxidized.
摘要翻译：提供一种非易失性半导体存储元件，其能够提高浮动栅极周围的绝缘体的绝缘性能并降低浮栅中的氧化金属超微粒子的比例。在制造非易失性半导体存储元件的方法中，所述非易失性半导体存储元件包括由几何可氧化材料制成的浮栅，所述浮栅具有Gibbs'形成自由能，用于在0℃至1200℃的范围内形成高于Si的氧化物，以及由易于氧化的材料的氧化物构成的绝缘体，该氧化物围绕浮动栅极并且具有等于或低于Si的能量，由几何可氧化材料制成的浮栅是通过使用物理成形法形成的，通过使用物理形成方法或化学成型方法形成易氧化材料，在形成栅极绝缘膜之后，在氧化气体和还原气体的混合气氛中，在 0℃至1200℃，同时控制混合气体和温度的混合比，使得只有几乎不可氧化的材料被还原，并且只有易氧化的氧化物太阳能被氧化。

26. 发明授权

US07326642B2 Method of fabricating semiconductor device using low dielectric constant material film 有权
标题翻译：使用低介电常数材料膜制造半导体器件的方法
公开(公告)号：US07326642B2
公开(公告)日：2008-02-05
申请号：US11275733
申请日：2006-01-26
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/4763
CPC分类号： H01L21/84 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/12 , H01L29/42384 , H01L29/66772 , H01L29/78603 , H01L29/78648 , H01L2224/2919 , H01L2224/32145 , H01L2924/00014
摘要： The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.
摘要翻译：半导体器件能够使用除硅以外的低介电常数材料膜来应对加速操作。设置由基板（11）形成的基板（10）和相对介电常数低于硅的低介电常数材料薄膜（12）。包括MOS晶体管（30）的半导体元件层粘附到基底（10）的表面上以进行堆叠。晶体管（30）通过使用岛状单晶硅膜（31）形成并埋入绝缘膜（15），（16）和（17）中。多层布线结构（18）形成在半导体元件层上并与晶体管（30）电连接。用作信号返回路径的电极（20）形成在基座（10）的背面上。代替在基座（10）上形成电极（20），电极（20A）可以布置在基座（10A）的后表面上，构成基座（10A）作为插入件。

27. 发明授权

US07303990B2 Nickel-silicon compound forming method, semiconductor device manufacturing method, and semiconductor device 失效
标题翻译：镍硅复合物形成方法，半导体器件制造方法和半导体器件
公开(公告)号：US07303990B2
公开(公告)日：2007-12-04
申请号：US11185157
申请日：2005-07-20
申请人： Mitsumasa Koyanagi , Jeoung Chill Shim , Hiroyuki Kurino
发明人： Mitsumasa Koyanagi , Jeoung Chill Shim , Hiroyuki Kurino
IPC分类号： H01L21/44
CPC分类号： H01L29/7834 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/66628
摘要： A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon.
摘要翻译：公开了一种镍硅化合物形成方法，其包括在仅硅和含硅化合物中的至少一种上形成镍，并且与仅含硅和含硅化合物中的至少一种一起进行镍的逐步加热。

28. 发明申请

US20050029643A1 Solid-state image sensor and its production method 失效
标题翻译：固态图像传感器及其制作方法
公开(公告)号：US20050029643A1
公开(公告)日：2005-02-10
申请号：US10494264
申请日：2002-11-05
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： G02B3/00 , H01L27/146 , H01L31/0232 , H01L21/00 , H01L23/02
CPC分类号： G02B3/0056 , G02B3/0075 , H01L23/481 , H01L27/14609 , H01L27/14618 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/14683 , H01L27/14685 , H01L31/0203 , H01L31/0232 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599
摘要： A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate (21) of the light-receiving element layer (20) corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (25a), (25b) and (26). The light-introducing layer (40), which includes the light-introducing cavity (42) and the quartz cap (51) for closing the cavity, is formed on the film (26). The microlenses (43) are incorporated into the cavity (42). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate (21) by way of the buried interconnections of the substrate (21) and then, derived to the outside of the image sensor by way of the output layer (10) or the interposer (10A).
摘要翻译：固态图像传感器具有可以容易地制造的芯片尺寸封装。元件形成区域形成在对应于像素区域的光接收元件层（20）的半导体衬底（21）中。半导体光接收元件（PD）形成在各个元件形成区域中并被透光绝缘膜（25a），（25b）和（26）覆盖。在膜（26）上形成有包括导光腔（42）和用于封闭空腔的石英盖（51）的光导入层（40）。微透镜（43）被结合到空腔（42）中。半导体光接收元件（PD）的电输出信号通过衬底（21）的埋入互连取出到衬底（21）的底部，然后通过输出层（10）或插入件（10A）的方式。

29. 发明授权

US07355238B2 Nonvolatile semiconductor memory device having nanoparticles for charge retention 失效
标题翻译：具有用于电荷保留的纳米颗粒的非易失性半导体存储器件
公开(公告)号：US07355238B2
公开(公告)日：2008-04-08
申请号：US11003421
申请日：2004-12-06
申请人： Masaaki Takata , Mitsumasa Koyanagi
发明人： Masaaki Takata , Mitsumasa Koyanagi
IPC分类号： H01L29/76
CPC分类号： H01L29/42332 , Y10S977/943
摘要： A nonvolatile semiconductor memory device including a source region and a drain region formed on a surface of a semiconductor substrate, a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region, a tunnel insulating film formed in contact with the channel-forming region, a charge retention layer formed adjacently to the tunnel insulating film, a gate insulating film formed adjacently to the charge retention layer, and a control gate formed adjacently to the gate insulating film. The charge retention layer includes an insulating matrix having, per nonvolatile semiconductor memory device, one conductive nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate.
摘要翻译：一种非易失性半导体存储器件，包括形成在半导体衬底的表面上的源极区域和漏极区域，形成为连接源极区域和漏极区域的沟道形成区域，以夹在源极区域和源极区域之间，漏极区域，与沟道形成区域形成的隧道绝缘膜，与隧道绝缘膜相邻形成的电荷保持层，与电荷保持层相邻形成的栅极绝缘膜，以及与栅极绝缘膜相邻形成的控制栅极栅极绝缘膜。电荷保持层包括绝缘矩阵，每个非易失性半导体存储器件具有由至少一个用作浮栅的单一元素物质或化合物制成的导电纳米颗粒。

30. 发明授权

US07265402B2 Solid-state image sensor including a microlens 失效
标题翻译：固态图像传感器包括微透镜
公开(公告)号：US07265402B2
公开(公告)日：2007-09-04
申请号：US10494264
申请日：2002-11-05
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： G02B3/0056 , G02B3/0075 , H01L23/481 , H01L27/14609 , H01L27/14618 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H01L27/14683 , H01L27/14685 , H01L31/0203 , H01L31/0232 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599
摘要： A solid-state image sensor has a chip-size package, which can be easily fabricated. The element-formation regions are formed in the semiconductor substrate (21) of the light-receiving element layer (20) corresponding to the pixel regions. The semiconductor light-receiving elements (PD) are formed in the respective element-formation regions and covered with the light-transmissive insulator films (25a), (25b) and (26). The light-introducing layer (40), which includes the light-introducing cavity (42) and the quartz cap (51) for closing the cavity, is formed on the film (26). The microlenses (43) are incorporated into the cavity (42). The electric output signals of the semiconductor light-receiving elements (PD) are taken out to the bottom of the substrate (21) by way of the buried interconnections of the substrate (21) and then, derived to the outside of the image sensor by way of the output layer (10) or the interposer (10A).
摘要翻译：固态图像传感器具有可以容易地制造的芯片尺寸封装。元件形成区域形成在对应于像素区域的光接收元件层（20）的半导体衬底（21）中。半导体光接收元件（PD）形成在各个元件形成区域中并被透光绝缘膜（25a），（25b）和（26）覆盖。在膜（26）上形成有包括导光腔（42）和用于封闭空腔的石英盖（51）的光导入层（40）。微透镜（43）被结合到空腔（42）中。半导体光接收元件（PD）的电输出信号通过衬底（21）的埋入互连取出到衬底（21）的底部，然后通过输出层（10）或插入件（10A）的方式。

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