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21. 发明申请

US20120163091A1 SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL 有权
标题翻译：存储细胞中的数据的半导体存储器件
公开(公告)号：US20120163091A1
公开(公告)日：2012-06-28
申请号：US13413779
申请日：2012-03-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
摘要翻译：存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数）比3）。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否存储器单元已达到i值（i <= k）阈值电压。

22. 发明申请

US20120044764A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION 有权
标题翻译：执行擦除操作的非易失性半导体存储器件
公开(公告)号：US20120044764A1
公开(公告)日：2012-02-23
申请号：US13052158
申请日：2011-03-21
申请人： Jun NAKAI , Noboru Shibata
发明人： Jun NAKAI , Noboru Shibata
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16 , G11C16/14 , G11C16/26 , G11C16/344 , G11C16/3445
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制单元。存储单元阵列包括以矩阵形式布置的多个存储单元。控制单元擦除存储单元的数据。控制单元在擦除操作期间根据第一命令中断存储器单元的擦除操作并保持中断前的擦除条件，并且根据第二命令基于保持的擦除条件恢复擦除操作。

23. 发明授权

US08098524B2 Semiconductor memory device capable of increasing writing speed 有权
标题翻译：能够提高写入速度的半导体存储器件
公开(公告)号：US08098524B2
公开(公告)日：2012-01-17
申请号：US13072240
申请日：2011-03-25
申请人： Noboru Shibata , Kenichi Imamiya
发明人： Noboru Shibata , Kenichi Imamiya
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C11/5628 , G11C16/0483 , G11C16/30
摘要： A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.
摘要翻译：存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。选择晶体管选择字线。控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储单元的写入，读取和擦除操作。选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压≥第一负电压）被提供给所选择的字线，并且第二电压被提供给非易失性存储器，在读取操作中选择字线。

24. 发明授权

US08077514B2 Semiconductor memory device capable of memorizing multivalued data 有权
标题翻译：能够存储多值数据的半导体存储器件
公开(公告)号：US08077514B2
公开(公告)日：2011-12-13
申请号：US12876845
申请日：2010-09-07
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C2211/5621 , G11C2211/5642 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。数据存储电路连接到位线并存储写入数据。当在存储单元阵列中的每个存储器单元中设置2k个阈值电压（k为自然数等于3或更大）时，数据存储电路包括至少一个静态锁存电路和多个动态锁存电路。控制电路通过将多个动态锁存电路之一中的数据移动到静态锁存电路来刷新数据，并且将静态锁存电路中的数据进一步移动到多个动态锁存电路之一。

25. 发明申请

US20110211395A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110211395A1
公开(公告)日：2011-09-01
申请号：US13036525
申请日：2011-02-28
申请人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
发明人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3436
摘要： A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.
摘要翻译：一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

26. 发明申请

US20100214852A1 SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL 有权
标题翻译：存储细胞中的数据的半导体存储器件
公开(公告)号：US20100214852A1
公开(公告)日：2010-08-26
申请号：US12775571
申请日：2010-05-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
摘要翻译：存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数）比3）。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否存储器单元已达到i值（i <= k）阈值电压。

27. 发明授权

US07663919B2 Semiconductor memory device capable of increasing writing speed 有权
标题翻译：能够提高写入速度的半导体存储器件
公开(公告)号：US07663919B2
公开(公告)日：2010-02-16
申请号：US12168457
申请日：2008-07-07
申请人： Noboru Shibata , Kenichi Imamiya
发明人： Noboru Shibata , Kenichi Imamiya
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C11/5628 , G11C16/0483 , G11C16/30
摘要： A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.
摘要翻译：存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。选择晶体管选择字线。控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储器单元的写入，读取和擦除操作。选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压> =第一负电压）被提供给所选字线，并且第二电压被提供给非 - 读取操作中选择的字线。

28. 发明授权

US07644342B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07644342B2
公开(公告)日：2010-01-05
申请号：US11414826
申请日：2006-05-01
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G06F11/10
CPC分类号： H03M13/6566 , G06F11/1068 , H03M13/152 , H03M13/158
摘要： An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010-1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010-1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528×8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).
摘要翻译： ECC电路（103）位于I / O端子（1040-1047）和页面缓冲器（1020-1027）之间。 ECC电路（103）包括：编码器，被配置为产生用于纠错的校验位（ECC），并将校验位附加到要写入多个存储单元区域的数据（1010-1017）;以及解码器，产生校验位（ECC），用于对从存储单元区域读出的数据进行纠错（1010-1017）。 ECC电路（103）将一组40个校验位（ECC）分配给4224 = 528×8的信息位长度，以通过并行处理8位数据执行编码和解码，其中将528位的数据定义为从一个存储单元区域（101j）写入和读出。

29. 发明申请

US20090141553A1 SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE 有权
标题翻译：具有电荷积累层和控制栅的存储单元提供的半导体存储器件
公开(公告)号：US20090141553A1
公开(公告)日：2009-06-04
申请号：US12365590
申请日：2009-02-04
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

30. 发明授权

US07509566B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07509566B2
公开(公告)日：2009-03-24
申请号：US11747225
申请日：2007-05-10
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M13/00 , G11C29/00 , G11C11/34
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

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