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    • 25. 发明申请
    • Document processing operation system
    • 文件处理操作系统
    • US20070176937A1
    • 2007-08-02
    • US11500914
    • 2006-08-09
    • Minoru KoshimizuYoshitsugu HiroseMasao WatanabeNaoki HayashiHiroyuki FunoHiroyuki Hotta
    • Minoru KoshimizuYoshitsugu HiroseMasao WatanabeNaoki HayashiHiroyuki FunoHiroyuki Hotta
    • G06T1/60
    • G06F3/0412G02F1/167G06F1/32
    • A document processing operation system includes: an image display holding medium that includes a display section for holding display of a document image rewritably and in a substantially no-power supply state; and a processing unit that processes document data in response to operation information of a user for the medium, wherein the medium further includes: an operation device that accepts operation input from a user; and an information providing section that provides operation information entered on the operation device to the processing unit, wherein the processing unit includes: a data processing section that performs processing preset in response to the operation information for data of a document whose display is held on the medium; a holding section that holds the operation information acquired from the medium; and a start command section that causes the data processing section to start processing in response to the held operation information.
    • 一种文件处理操作系统,包括:图像显示保持介质,其包括用于保持文件图像可重写地且基本上不供电状态的显示的显示部分; 以及处理单元,其响应于用于所述介质的用户的操作信息来处理文档数据,其中所述介质还包括:操作设备,其接受来自用户的操作输入; 以及信息提供部,其将输入到所述操作装置的操作信息提供给所述处理单元,其中,所述处理单元包括:数据处理部,其响应于用于显示被保持在所述操作信息上的文档的数据的操作信息进行预设的处理 中; 保持部,其保持从所述介质获取的操作信息; 以及开始命令部,其使得数据处理部根据所保持的操作信息开始处理。
    • 30. 发明授权
    • Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro
    • 半导体集成电路,半导体集成电路和功能宏布局设计中的布线方法
    • US06727120B2
    • 2004-04-27
    • US10085009
    • 2002-03-01
    • Masahiro FukuiNaoki Hayashi
    • Masahiro FukuiNaoki Hayashi
    • H01L2182
    • H01L23/5225H01L27/118H01L2924/0002H01L2924/00
    • In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.
    • 在并联布置6位互连线时,例如交替地放置具有高信号变化频率的三个低阶位的互连线和具有低信号变化频率的三个高位的互连线,使得每个 用于较低位的互连线被用于高阶位的互连线夹在中间。 通过这种布局,用于高阶位的互连线像用于低阶位的互连线的屏蔽线一样。 这有效地抑制了由于通过用于较低位的互连线传播的信号的变化和通过用于较高位的互连线传播到相对相位的信号而导致的信号传播延迟的增加,而不增加面积。