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    • 21. 发明授权
    • Method and system for handwriting-based launch of an application
    • 用于基于手写的应用程序启动的方法和系统
    • US08799798B2
    • 2014-08-05
    • US12796814
    • 2010-06-09
    • Hidenobu Ito
    • Hidenobu Ito
    • G06F3/048G06F3/033G06F17/30
    • G06F17/30867G06F3/04883G06F17/3025G06F17/30259G06F17/3079G06F17/30864G06F17/30997
    • Methods and systems for providing navigation assistance on a mobile device are provided. A method may include analyzing handwriting data to recognize one or more objects depicted in the handwriting data. The method may further include determining if one or more applications are associated with the handwriting data based on the one or more objects recognized in the handwriting data. If one application is determined to be associated with the handwriting data, the one application may be launched. If two or more applications are determined to be associated with the handwriting data, information allowing a user to select an application to launch from the two or more applications may be displayed.
    • 提供了用于在移动设备上提供导航辅助的方法和系统。 方法可以包括分析手写数据以识别手写数据中描绘的一个或多个对象。 该方法还可以包括基于手写数据中识别的一个或多个对象来确定一个或多个应用是否与手写数据相关联。 如果确定一个应用程序与手写数据相关联,则可以启动一个应用程序。 如果确定两个或多个应用程序与手写数据相关联,则可以显示允许用户选择从两个或更多个应用程序启动的应用程序的信息。
    • 22. 发明申请
    • APPARATUS AND METHOD FOR SWITCHING CONNECTION TO A COMMUNICATION NETWORK
    • 用于切换到通信网络的连接的装置和方法
    • US20120269193A1
    • 2012-10-25
    • US13431010
    • 2012-03-27
    • Zhaogong GuoKazuaki NimuraYosuke NakamuraKoichi YasakiHidenobu Ito
    • Zhaogong GuoKazuaki NimuraYosuke NakamuraKoichi YasakiHidenobu Ito
    • H04L12/56
    • H04L49/35
    • An apparatus includes first and second processors, a common memory, and a switch. The first processor executes an operating system, connects to a communication network and communicates with the communication network. The second processor operates independently of the operating system, connects to the communication network, and communicates with the communication network. The second processor writes, in the common memory, communication setting information being used by the second processor when the switch switches the connection destination from the second processor to the first processor. The first processor acquires the communication setting information, and sets the acquired communication setting information to the first processor. The switch switches the connection destination of the communication network from the second processor to the first processor after the communication setting information has been set to the first processor.
    • 一种装置包括第一和第二处理器,公共存储器和开关。 第一处理器执行操作系统,连接到通信网络并与通信网络进行通信。 第二处理器独立于操作系统操作,连接到通信网络,并与通信网络进行通信。 第二处理器在公共存储器中写入当交换机将连接目的地从第二处理器切换到第一处理器时由第二处理器使用的通信设置信息。 第一处理器获取通信设置信息,并将所获取的通信设置信息设置到第一处理器。 在将通信设置信息设置为第一处理器之后,交换机将通信网络的连接目的地从第二处理器切换到第一处理器。
    • 25. 发明授权
    • Memory product controller, memory product control method, and memory product
    • 内存产品控制器,内存产品控制方法和内存产品
    • US07340559B2
    • 2008-03-04
    • US11256932
    • 2005-10-25
    • Hidenobu ItoKatsutoshi YanoIsamu Yamada
    • Hidenobu ItoKatsutoshi YanoIsamu Yamada
    • G06F12/00G06F13/00G06F13/28G06F3/00G11C7/00
    • G06K7/0008G06K17/00
    • To provide a memory product controller, a memory product control method, and a memory product storing a computer program, capable of realizing a multi-function memory product, without increasing the cost, by grouping a plurality of memory products. In a memory product controller, information identifying a memory product and an operating condition of the memory product are stored in association with information identifying a group, and when reading/writing is performed on one memory product belonging to a predetermined group by a reader/writer for a memory product, reference is made to an operating condition storage unit, and when other memory products having the similar operating condition are present in the same group, instruction information to perform reading or writing on one or a plurality of other memory products belonging to the same group and having the similar operating condition is transmitted to the reader/writer.
    • 通过分组多个存储器产品来提供存储产品控制器,存储器产品控制方法和存储计算机程序的存储器产品,其能够实现多功能存储器产品而不增加成本。 在存储器产品控制器中,与识别组的信息相关联地存储识别存储器产品的信息和存储器产品的操作条件,并且当由读写器对属于预定组的一个存储器产品执行读/写时 对于存储器产品,参考操作条件存储单元,并且当具有类似操作条件的其他存储器产品存在于同一组中时,对属于该存储器的一个或多个其他存储器产品执行读取或写入的指令信息 具有类似操作条件的相同组被传送到读/写器。
    • 27. 发明申请
    • CONTROL CIRCUIT OF DC-DC CONVERTER AND CONTROL METHOD THEREOF
    • DC-DC转换器的控制电路及其控制方法
    • US20060071651A1
    • 2006-04-06
    • US11025134
    • 2004-12-30
    • Hidenobu Ito
    • Hidenobu Ito
    • H02M3/156
    • H02M3/1588Y02B70/1466
    • There are provided a control circuit of a DC-DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption at the stop of power supply, and a control method thereof. While a power supply stop signal is at low level, a control part controls an NMOS transistor according to the output signals of a comparator and a flip-flop circuit. While the power supply stop signal is at high level, the control part masks a reverse current detection signal and the output signal of the flip-flop circuit to control the NMOS transistor according to a detection signal of a comparator. When a choke coil current is reversely flowed and an output voltage is lowered to an output reference voltage corresponding to a reference voltage, the NMOS transistor is brought to the non-conductive state to regenerate the electric power to an input terminal.
    • 提供了一种同步整流系统的DC-DC转换器的控制电路及其控制方法,该控制电路能够在停电时实现低功耗的输出电压的快速降低。 当电源停止信号处于低电平时,控制部分根据比较器和触发器电路的输出信号来控制NMOS晶体管。 当电源停止信号处于高电平时,控制部分屏蔽反向电流检测信号和触发器电路的输出信号,以根据比较器的检测信号控制NMOS晶体管。 当扼流线圈电流反向流动并且输出电压降低到与参考电压相对应的输出参考电压时,NMOS晶体管变为非导通状态,以将电力再生为输入端子。
    • 29. 发明授权
    • Bias voltage supplying circuit
    • 偏压供电电路
    • US5034677A
    • 1991-07-23
    • US572134
    • 1990-08-22
    • Hidenobu ItoFumihiko Sato
    • Hidenobu ItoFumihiko Sato
    • H03F1/30G05F3/22G05F3/26G05F3/30
    • G05F3/22Y10S323/901
    • A bias voltage supplying circuit for supplying a bias voltage includes first and second PNP type transistors having emitters coupled to a first power source terminal and bases connected to each other, where the first PNP type transistor has a collector coupled to the base thereof, first and second NPN type transistors having collectors respectively connected to collectors of the first and second PNP type transistors, emitters coupled to a second power source terminal and bases connected to each other, where the second NPN type transistor has the collector connected to the base thereof, and a diode part coupled between the emitter of the second PNP type transistor and the base of the second NPN type transistor. The diode part has an anode end coupled to the emitter of the second PNP type transistor and a cathode end coupled to the base of the second NPN type transistor, and the diode part has a forward voltage drop V.sub.D which is less than a voltage V.sub.S across the first and second power source terminals. The voltage V.sub.S is less than a sum of the forward voltage drop V.sub.D and a base-emitter voltage V.sub.BE of the second NPN type transistor.