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    • 27. 发明授权
    • Memory management and protection system for virtual memory in computer
system
    • 计算机系统虚拟内存的内存管理和保护系统
    • US5890189A
    • 1999-03-30
    • US753944
    • 1996-12-03
    • Hiroshi NozueMitsuo SaitoKenichi MaedaShigehiro AsanoToshio OkamotoShin SunghoHideo Segawa
    • Hiroshi NozueMitsuo SaitoKenichi MaedaShigehiro AsanoToshio OkamotoShin SunghoHideo Segawa
    • G06F12/10G06F12/14G06F12/00
    • G06F12/1458G06F12/109G06F12/1483G06F12/1491G06F2212/656
    • A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
    • 一种用于实现高速执行的存储器管理和保护系统,以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中,根据标识逻辑地址空间中的段的段标识符,允许存储器访问,以及每个区段中的区域的存储器保护信息,包括目标权限,以指示从存储器访问的指定的权限 区域,以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者,可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问,每个地址表条目存储多个程序号,标识被允许访问存储在每个地址表条目中的逻辑地址的程序, 将搜索与当前节目号匹配的那个。 此外,优选地,在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间,而不会在相邻分配的地址区域之间发生任何重叠。
    • 28. 发明授权
    • Method for managing virtual address space at improved space utilization
efficiency
    • 在提高空间利用效率的情况下管理虚拟地址空间的方法
    • US5826057A
    • 1998-10-20
    • US5371
    • 1993-01-15
    • Toshio OkamotoHideo SegawaMitsuo SaitoOsamu Wakamori
    • Toshio OkamotoHideo SegawaMitsuo SaitoOsamu Wakamori
    • G06F12/08G06F12/02G06F12/10
    • G06F12/0292G06F12/109
    • A method for managing virtual address space in which programs designed for smaller virtual address spaces in the multiple virtual memory scheme can be collectively allocated to a single enlarged virtual address space in the single virtual memory scheme efficiently, without requiring any change in the programs themselves, such that the entire virtual address space becomes available in the compatible mode. In the method, the effective addresses to be used during an execution of a program designed for a smaller address space are calculated by combining an appropriate address base for this program specifying upper bits of the effective address and lower bits of the virtual addresses for a region of the enlarged address space to which this program is allocated. The address base may be replaced by the upper bits of the starting address of the program in the enlarged address space which are retained throughout the effective address calculation. The method may use a compatible mode address region to be used in executing a program designed for a smaller address space which has virtual addresses identical to those to which this program is designed to be allocated in the smaller address space.
    • 一种用于管理虚拟地址空间的方法,其中可以有效地在多个虚拟存储器方案中为较小的虚拟地址空间设计的程序集中地分配给单个虚拟存储器方案中的单个放大虚拟地址空间,而不需要程序本身的任何改变, 使得整个虚拟地址空间在兼容模式下变得可用。 在该方法中,通过组合用于指定有效地址的较高比特和该区域的虚拟地址的较低比特的该程序的适当地址基来计算在执行针对较小地址空间的程序执行期间使用的有效地址 扩展的地址空间被分配给该程序。 地址库可以被放大的地址空间中的程序的起始地址的较高位代替,这些地址在整个有效地址计算中被保留。 该方法可以使用兼容模式地址区域来执行为较小地址空间而设计的程序,该地址空间的虚拟地址与在该较小地址空间中被设计为分配的虚拟地址相同。
    • 29. 发明授权
    • Method for forming an image on a silver halide color photographic
material
    • 在卤化银彩色照相材料上形成图像的方法
    • US5650264A
    • 1997-07-22
    • US593174
    • 1996-02-01
    • Kiyoshi KawaiMitsuo Saito
    • Kiyoshi KawaiMitsuo Saito
    • G03C1/035G03C5/08G03C7/30G03C7/42G03C7/44G03C5/00
    • G03C7/3022G03C7/44
    • There is disclosed a method for forming an image by processing a silver halide color photographic material having at least one silver halide emulsion layer on a support, wherein at least one layer of the silver halide emulsion layers of said color photographic material comprises silver halide grains which is high in silver chloride content and whose silver chloride content is 80 mol % or more; said silver halide grains are tabular silver halide grains having (100) planes as main planes; and said color photographic material is processed with the replenishment rate of a replenisher having a bleaching capacity in a desilvering step being 150 ml or less per m.sup.2 of the photographic material. The method for forming an image on a silver halide color photographic material of the present invention is excellent in delivering characteristics, even when the replenishment rate of bleach-fix solution is reduced remarkably.
    • 公开了一种通过在载体上处理具有至少一个卤化银乳剂层的卤化银彩色照相材料来形成图像的方法,其中所述彩色照相材料的至少一层卤化银乳剂层包含卤化银颗粒,卤化银颗粒 氯化银含量高,氯化银含量为80摩尔%以上; 所述卤化银颗粒是具有(100)面作为主平面的片状卤化银颗粒; 并且所述彩色照相材料在除沫步骤中具有漂白能力的补充量的补充速率为每平方米照相材料为150毫升或更少。 在本发明的卤化银彩色照相材料上形成图像的方法即使在漂白固定液的补充量显着降低的情况下也具有优异的输送特性。
    • 30. 发明授权
    • Cache memory system for multiple processors with collectively arranged
cache tag memories
    • 具有共同设置的高速缓存标签存储器的多个处理器的缓存存储器系统
    • US5634027A
    • 1997-05-27
    • US979806
    • 1992-11-20
    • Mitsuo Saito
    • Mitsuo Saito
    • G06F12/08G06F12/02
    • G06F12/0859G06F12/0848
    • A cache memory system capable of realizing a high level performance and a high speed processing with a simple control. The system may use a plurality of processing units and a plurality of corresponding cache memory units, where all the cache tag memory units of the cache memory units are collectively arranged in relation to the primary processing unit which carries out a memory access address calculation. The system may also use a refilling control such that a new refilling operation for a newly occurred cache miss in the primary cache memory unit is started in parallel to another refilling operation for a previously occurred cache miss in the primary cache memory unit before that another refilling operation is completed. The system may also use a refilling control such that the refilling operation is started by making an access to the secondary memory unit with a starting address at which the cache miss occurred in the primary cache memory unit, and continued by making subsequent accesses to the secondary memory unit with addresses obtained by adding an increment to the starting address one by one.
    • 一种能够通过简单控制实现高水平性能和高速处理的高速缓冲存储器系统。 系统可以使用多个处理单元和多个相应的高速缓冲存储器单元,其中高速缓存存储器单元的所有高速缓存标签存储单元相对于执行存储器访问地址计算的主处理单元共同排列。 系统还可以使用重新填充控制,使得在初级高速缓存存储器单元中的新发生的高速缓存未命中的新的重新填充操作与首次高速缓冲存储器单元中先前发生的高速缓存未命中的另一个再填充操作并行地开始,之后再次再填充 操作完成。 该系统还可以使用重新填充控制,使得通过以一次高速缓存存储器单元中发生高速缓存未命中的起始地址访问辅助存储器单元来开始重新填充操作,并且继续通过对次级存储器进行后续访问 存储单元,具有通过逐个增加起始地址而获得的地址。