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21. 发明授权

US08759172B2 Etch stop layer formation in metal gate process 失效
标题翻译：在金属栅极工艺中形成蚀刻停止层
公开(公告)号：US08759172B2
公开(公告)日：2014-06-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

22. 发明申请

US20140001575A1 SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES 有权
标题翻译：具有不同栅极氧化物厚度的半导体器件
公开(公告)号：US20140001575A1
公开(公告)日：2014-01-02
申请号：US13534012
申请日：2012-06-27
申请人： Charlotte DeWan Adams , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Shahab Siddiqui
发明人： Charlotte DeWan Adams , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Shahab Siddiqui
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/42364 , H01L29/66545 , H01L29/66795
摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.
摘要翻译：制造具有不同厚度栅极氧化物的多个finFET器件的方法。该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

23. 发明申请

US20130277764A1 Etch Stop Layer Formation In Metal Gate Process 失效
标题翻译：金属浇口工艺中的蚀刻停止层形成
公开(公告)号：US20130277764A1
公开(公告)日：2013-10-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

24. 发明授权

US08581351B2 Replacement gate with reduced gate leakage current 有权
标题翻译：栅极泄漏电流降低的替代栅极
公开(公告)号：US08581351B2
公开(公告)日：2013-11-12
申请号：US13006656
申请日：2011-01-14
申请人： Takashi Ando , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
发明人： Takashi Ando , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.
摘要翻译：提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

25. 发明申请

US20120181616A1 STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY 失效
标题翻译：高k金属门技术的镀层结构与方法
公开(公告)号：US20120181616A1
公开(公告)日：2012-07-19
申请号：US13006642
申请日：2011-01-14
申请人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.
摘要翻译：提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。等离子体氮化的nFET阈值电压调节的高k栅介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化的pFET阈值电压调节的高k栅介质层部分包括多达15个原子％N2和位于其中的pFET阈值电压调节物质。

26. 发明申请

US20120068261A1 Replacement Metal Gate Structures for Effective Work Function Control 有权
标题翻译：更换金属门结构，实现有效的工作功能控制
公开(公告)号：US20120068261A1
公开(公告)日：2012-03-22
申请号：US12885592
申请日：2010-09-20
申请人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
发明人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823842
摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
摘要翻译：在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。阻挡金属层可以直接沉积在栅极介电层上。图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。或者，第一类功函数层可以直接沉积在栅介电层上。图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。导电材料填充和平坦化形成双功能功能替代栅极结构。

27. 发明授权

US08643115B2 Structure and method of Tinv scaling for high κ metal gate technology 失效
标题翻译：用于高kappa金属栅极技术的Tinv缩放的结构和方法
公开(公告)号：US08643115B2
公开(公告)日：2014-02-04
申请号：US13006642
申请日：2011-01-14
申请人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L27/092
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.
摘要翻译：提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个原子％N2和位于其中的pFET阈值电压调节物质。

28. 发明授权

US08552502B2 Structure and method to make replacement metal gate and contact metal 有权
标题翻译：用于替换金属栅极和接触金属的结构和方法
公开(公告)号：US08552502B2
公开(公告)日：2013-10-08
申请号：US13427963
申请日：2012-03-23
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
IPC分类号： H01L27/12
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。层间电介质存在于半导体衬底上。层间电介质包括到p型和n型半导体器件的源区和漏区的互连。互连由钛和铝构成的金属层和由铝组成的金属填充物构成。本公开还提供了形成上述结构的方法。

29. 发明申请

US20130105879A1 NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
标题翻译：使用高K门电介质和金属门的非易失性存储器结构
公开(公告)号：US20130105879A1
公开(公告)日：2013-05-02
申请号：US13326767
申请日：2011-12-15
申请人： Nicolas Breil , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon
发明人： Nicolas Breil , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28273 , H01L21/0228 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/11546 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/7881
摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
摘要翻译：用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和用于非易失性随机存取存储器（NVRAM）器件的高k隧道电介质）同时形成在半导体衬底上。随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。沉积并图案化平坦化介电层，并且去除一次性材料部分。控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

30. 发明授权

US08241981B1 Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor 失效
标题翻译：制造深沟槽（DT）金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US08241981B1
公开(公告)日：2012-08-14
申请号：US13017108
申请日：2011-01-31
申请人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
发明人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/1087 , H01L28/40 , H01L29/66181
摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.
摘要翻译：一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

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