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21. 发明申请

US20110031503A1 DEVICE WITH STRESSED CHANNEL 审中-公开
标题翻译：具有应力通道的设备
公开(公告)号：US20110031503A1
公开(公告)日：2011-02-10
申请号：US12538627
申请日：2009-08-10
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
IPC分类号： H01L29/161 , H01L27/092 , H01L21/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.
摘要翻译：公开了一种FET器件，其包含各自具有延伸部的源极和漏极。源极和漏极及其延伸部分由包含Ge或C的外延材料组成。外延材料和Si衬底具有不同的晶格常数，因此源极和漏极及其延伸部分在沟道上赋予应力状态。对于PFET器件，外延材料可以是SiGe或Ge，并且沟道可以处于压应力的压缩状态。对于NFET器件，外延材料可以是SiC，并且沟道可以处于应力的拉伸状态。还公开了一种用于制造FET器件的方法。可以在Si衬底中形成第一凹陷到栅极的相对侧上的第一深度。用第一外延材料外延地填充第一次衰退。然后，可以在Si衬底中形成比第一深度更大的第二深度的第二凹陷。接下来，可以用与第一外延材料相同的材料的第二外延材料填充第二凹陷。选择外延材料具有与Si衬底不同的晶格常数，并且因此在沟道上施加应力状态。

22. 发明申请

US20070267671A1 TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开
标题翻译：具有仅一个方向的横向延伸的TRENCH电容器及相关方法
公开(公告)号：US20070267671A1
公开(公告)日：2007-11-22
申请号：US11383861
申请日：2006-05-17
申请人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
发明人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.
摘要翻译：公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。

23. 发明授权

US07084449B2 Microelectronic element having trench capacitors with different capacitance values 失效
标题翻译：具有不同电容值的沟槽电容器的微电子元件
公开(公告)号：US07084449B2
公开(公告)日：2006-08-01
申请号：US10710146
申请日：2004-06-22
申请人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
发明人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/10894 , H01L29/945
摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.
摘要翻译：提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处，并且第二电容器的顶部设置在距离主表面的第二深度处。

24. 发明授权

US06686668B2 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask 有权
公开(公告)号：US06686668B2
公开(公告)日：2004-02-03
申请号：US09764833
申请日：2001-01-17
申请人： Larry A. Nesbit , Johnathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
发明人： Larry A. Nesbit , Johnathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L21/76895 , H01L21/76897 , H01L27/10888
摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

25. 发明授权

US06348388B1 Process for fabricating a uniform gate oxide of a vertical transistor 失效
标题翻译：制造垂直晶体管的均匀栅极氧化物的工艺
公开(公告)号：US06348388B1
公开(公告)日：2002-02-19
申请号：US09668638
申请日：2000-09-20
申请人： Johnathan E. Faltermeier , Ulrike Gruening , Suryanarayan G. Hegde , Rajarao Jammy , Brian S. Lee , Helmut H. Tews
发明人： Johnathan E. Faltermeier , Ulrike Gruening , Suryanarayan G. Hegde , Rajarao Jammy , Brian S. Lee , Helmut H. Tews
IPC分类号： H01L21336
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10876 , H01L29/045 , H01L29/4236 , H01L29/66666 , H01L29/7813 , H01L29/7827 , Y10S438/931
摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.
摘要翻译：一种用于制造垂直晶体管的栅极氧化物的工艺。在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。沟槽侧壁包括<100>晶面和<110>晶面。接下来，在沟槽侧壁上形成均匀厚度的牺牲层。在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入沟槽侧壁的<110>晶面，而不是注入沟槽侧壁的<100>晶面。然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

26. 发明授权

US6150670A Process for fabricating a uniform gate oxide of a vertical transistor 失效
公开(公告)号：US6150670A
公开(公告)日：2000-11-21
申请号：US450546
申请日：1999-11-30
申请人： Johnathan E. Faltermeier , Ulrike Gruening , Suryanarayan G. Hegde , Rajarao Jammy , Brian S. Lee , Helmut H. Tews
发明人： Johnathan E. Faltermeier , Ulrike Gruening , Suryanarayan G. Hegde , Rajarao Jammy , Brian S. Lee , Helmut H. Tews
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/04 , H01L29/12 , H01L29/423 , H01L29/78 , H01L27/108
CPC分类号： H01L21/28211 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10876 , H01L29/045 , H01L29/66666 , H01L29/7827 , H01L21/26506 , H01L27/10864 , H01L29/4236 , H01L29/7813 , Y10S438/931
摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

27. 发明授权

US08525186B2 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
标题翻译：在绝缘体上硅（SOI）晶片上形成具有嵌入和刻面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构
公开(公告)号：US08525186B2
公开(公告)日：2013-09-03
申请号：US13101267
申请日：2011-05-05
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

28. 发明申请

US20120280250A1 SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS 失效
标题翻译：间隔器作为CMOS熔体中的现场掺杂的硬掩模方案
公开(公告)号：US20120280250A1
公开(公告)日：2012-11-08
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译：一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁结构体。在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。还描述了通过上述方法形成的结构。

29. 发明申请

US20110175164A1 DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS 有权
标题翻译：非均匀应变晶体管的器件结构，布局和制造方法
公开(公告)号：US20110175164A1
公开(公告)日：2011-07-21
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

30. 发明申请

US20110101455A1 FINFET SPACER FORMATION BY ORIENTED IMPLANTATION 有权
标题翻译：通过面向植入形成的FINFET间隙
公开(公告)号：US20110101455A1
公开(公告)日：2011-05-05
申请号：US12611444
申请日：2009-11-03
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/26586 , H01L21/823431 , H01L29/66803 , H01L29/785
摘要： A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.
摘要翻译：通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

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