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21. 发明授权

US5910913A Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5910913A
公开(公告)日：1999-06-08
申请号：US124794
申请日：1998-07-30
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C8/08 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C8/08 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.
摘要翻译：非易失性半导体存储器的每个存储单元基本上由仅包括具有浮置栅电极的MOSFET的单晶体管型存储单元组成。当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。特别是由于用于字线的负电压，可以降低编程数据时的漏极电压，从而可以减轻沟道部分的栅极氧化膜的劣化。

22. 发明授权

US5828600A Non-volatile semiconductor memory 失效
公开(公告)号：US5828600A
公开(公告)日：1998-10-27
申请号：US739156
申请日：1996-10-30
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume
IPC分类号： G11C8/08 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C16/02
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C8/08 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

23. 发明授权

US5532971A Nonvolatile semiconductor memory having enhanced speed for erasing and programming 失效
标题翻译：具有提高擦除和编程速度的非易失性半导体存储器
公开(公告)号：US5532971A
公开(公告)日：1996-07-02
申请号：US354639
申请日：1994-12-13
申请人： Toshihiro Tanaka , Masataka Kato , Keiichi Yoshida , Hitoshi Kume , Yoshinobu Nakagome , Katsutaka Kimura
发明人： Toshihiro Tanaka , Masataka Kato , Keiichi Yoshida , Hitoshi Kume , Yoshinobu Nakagome , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/12 , G11C8/00 , G11C11/34
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.
摘要翻译：提供了一种布置，以提高由单个电源电压驱动的非易失性半导体存储器的擦除和编程操作的速度，并且减少构成子字解码器电路的晶体管的数量，从而使器件的尺寸最小化。为此，在驱动字线Wi1-Wij的子字解码器电路WDi1-WDij中，将从第一地址线组产生的块选择地址线Bip和Bin用作控制电压的逆变器电路的电源电压字线和从第二地址线组产生的选通选择地址线Gj用于栅极输入线。

24. 发明授权

US5467309A Semiconductor nonvolatile memory device having reduced switching overhead time on the program mode 失效
标题翻译：半导体非易失性存储器件在编程模式下具有减少的开关开销时间
公开(公告)号：US5467309A
公开(公告)日：1995-11-14
申请号：US252604
申请日：1994-06-01
申请人： Toshihiro Tanaka , Masataka Kato , Hitoshi Kume , Keisuke Ogura , Tetsuo Adachi
发明人： Toshihiro Tanaka , Masataka Kato , Hitoshi Kume , Keisuke Ogura , Tetsuo Adachi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： A semiconductor nonvolatile memory device capable of reducing the overhead time of the time required for switching the verify operation and the verify operation itself. In the semiconductor nonvolatile memory device which operates to program the threshold of the memory cells on the basis of a plurality of repetitive operations, the mincing width .increment.Vth of the variation of the threshold of the memory cells relative to one operation for changing the threshold (applying the program pulse) is expressed by .increment.Vth=Kvth.multidot.log (t2/t1), and the ratio (t2/t1) between the program pulse widths is expressed by (t2/t1)=10E(.increment.Vth/Kvth). The pulses in which the difference .increment.Vth of the variation of the threshold of the memory cells is made constant, and the pulse width is increased as the repetition number increases are applied to the memory cells, thereby reducing the application number of program pulses.
摘要翻译：一种半导体非易失性存储器件，其能够减少切换验证操作和验证操作本身所需的时间的开销时间。在基于多个重复操作对存储器单元的阈值进行编程的半导体非易失性存储器件中，存储单元的阈值相对于用于改变阈值的一个操作的变化的切割宽度INCREMENT Vth 应用编程脉冲）由INCREMENT Vth = Kvthxlog（t2 / t1）表示，并且编程脉冲宽度之间的比率（t2 / t1）由（t2 / t1）= 10E（INCREMENT Vth / Kvth）表示。使存储器单元的阈值的变化的差INCREMENT Vth变为恒定，并且脉冲宽度随着重复数量的增加而增加，从而减少编程脉冲的应用次数。

25. 发明授权

US5446690A Semiconductor nonvolatile memory device 失效
标题翻译：半导体非易失性存储器件
公开(公告)号：US5446690A
公开(公告)日：1995-08-29
申请号：US249383
申请日：1994-05-25
申请人： Toshihiro Tanaka , Masataka Kato , Toshio Sasaki , Hitoshi Kume , Hiroaki Kotani , Kazunori Furusawa
发明人： Toshihiro Tanaka , Masataka Kato , Toshio Sasaki , Hitoshi Kume , Hiroaki Kotani , Kazunori Furusawa
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C11/34
CPC分类号： G11C16/10
摘要： A semiconductor nonvolatile memory device in which the states of memory cells are determined with respect to each of all data lines in a nonvolatile memory device so as to perform control such as continuation and suspension of programming automatically. Memory cell arrays in which nonvolatile semiconductor memory cells are arranged in an array form, word lines W1 and W2 to which control gates of a plurality of memory cell groups (sectors) are connected in common and data lines to which drains of a plurality of memory cells are connected in common are included, and there are possessed of a precharging circuit, a data hold circuit having a sense amplifier function and a data latch function and a memory cell state detecting circuit for each of said data lines. Reprogramming is made at the same time with respect to memory cells (sector) connected to the same word line. During reprogramming operation, the state of memory cells is read out at the same time with all of the data lines, and continuation and suspension of the reprogramming operation are controlled in the device only based on the information.
摘要翻译：一种半导体非易失性存储器件，其中相对于非易失性存储器件中的所有数据线中的每一条确定存储器单元的状态，以便自动执行诸如程序的继续和暂停的控制。以阵列形式布置非易失性半导体存储单元的存储单元阵列，多个存储单元组（扇区）的控制栅极连接到多个存储器的漏极的公共数据线和数据线的字线W1和W2 包括单元相连，并且具有预充电电路，具有读出放大器功能和数据锁存功能的数据保持电路以及用于每个所述数据线的存储单元状态检测电路。相对于连接到同一字线的存储单元（扇区），同时进行重新编程。在重新编程操作期间，与所有数据线同时读出存储单元的状态，并且仅基于该信息在设备中控制重新编程操作的继续和暂停。

26. 发明授权

US5872734A Semiconductor nonvolatile memory device and computer system using the same 失效
标题翻译：半导体非易失性存储器件和使用其的计算机系统
公开(公告)号：US5872734A
公开(公告)日：1999-02-16
申请号：US60364
申请日：1998-04-15
申请人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
发明人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
IPC分类号： G11C17/00 , G11C7/10 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C7/103 , G11C16/26
摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.
摘要翻译：一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。施加低于从外部施加的电源电压Vcc的读取选择字线电压Vrw，并且在非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差减小以使较高的阈值电压VthH接近于较低的阈值电压VthL。此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

27. 发明授权

US5748532A Semiconductor nonvolatile memory device and computer system using the same 失效
标题翻译：半导体非易失性存储器件和使用其的计算机系统
公开(公告)号：US5748532A
公开(公告)日：1998-05-05
申请号：US677842
申请日：1996-07-10
申请人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
发明人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
IPC分类号： G11C17/00 , G11C7/10 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C7/103 , G11C16/26
摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of the nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.
摘要翻译：一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。施加低于从外部施加的电源电压Vcc的读取选择的字线电压Vrw，并且非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差为减小以使较高的阈值电压VthH接近于较低的阈值电压VthL。此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

28. 发明授权

US5581508A Semiconductor memory having sub-word line replacement 失效
标题翻译：具有子字线更换的半导体存储器
公开(公告)号：US5581508A
公开(公告)日：1996-12-03
申请号：US352619
申请日：1994-12-09
申请人： Toshio Sasaki , Toshihiro Tanaka , Atsushi Nozoe , Hitoshi Kume
发明人： Toshio Sasaki , Toshihiro Tanaka , Atsushi Nozoe , Hitoshi Kume
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/804 , G11C29/806 , G11C29/808
摘要： In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.
摘要翻译：在具有通过主字线和字线分类的行解码器的半导体存储装置中，不增加备用主字线的数量，增加了缺陷的备用线的数量。冗余电路的面积被最小化以提高芯片的产量。每个包括多个存储器单元的正常和备用存储器块被分割，使得即使在与多个正常主字线相关联的缺陷地址发生时，也可以不增加备用主字线的数量来进行替换。

29. 发明授权

US5422856A Non-volatile memory programming at arbitrary timing based on current requirements 失效
标题翻译：基于当前要求的任意定时的非易失性存储器编程
公开(公告)号：US5422856A
公开(公告)日：1995-06-06
申请号：US203303
申请日：1994-03-01
申请人： Toshio Sasaki , Toshihiro Tanaka , Masataka Kato
发明人： Toshio Sasaki , Toshihiro Tanaka , Masataka Kato
IPC分类号： G06F12/06 , G06F12/00 , G11C16/02 , G11C16/10 , G11C17/00 , G11C8/00
CPC分类号： G11C16/102
摘要： To effect erase and program operations, i.e., rewrite of the non-volatile memory device efficiently with small electric power consumption and at high speed, a plurality of memory blocks that have a plurality of sectors and that each include a plurality of non-volatile memory cells are connected to buffer memories having at least the same memory capacity as a sector, and a read/write circuit generates internal addresses and timing for selecting sectors according to the external address and timing signals to control the read-out and rewrite of data between the sectors corresponding to the internal addresses and the buffer memories corresponding to the sectors, wherein the read/write circuit selects the sectors at timings shifted from one another and erases or programs the data in the selected sector in order to rewrite the data.
摘要翻译：为了实现擦除和编程操作，即以小功耗和高速度有效地重写非易失性存储器件，具有多个扇区的多个存储器块，并且每个存储块中的每一个包括多个非易失性存储器单元被连接到具有至少与扇区相同的存储容量的缓冲存储器，并且读/写电路根据外部地址和定时信号产生用于选择扇区的内部地址和定时，以控制数据的读出和重写对应于内部地址的扇区和对应于扇区的缓冲存储器，其中读/写电路在彼此偏移的定时中选择扇区，并擦除或编程所选扇区中的数据，以重写数据。

30. 发明授权

US06288941B1 Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks 失效
标题翻译：具有划分为存储块的存储单元阵列的电可擦除半导体非易失性存储器件
公开(公告)号：US06288941B1
公开(公告)日：2001-09-11
申请号：US08379020
申请日：1995-01-27
申请人： Kouichi Seki , Toshihiro Tanaka , Hitoshi Kume , Takeshi Wada , Tadashi Muto
发明人： Kouichi Seki , Toshihiro Tanaka , Hitoshi Kume , Takeshi Wada , Tadashi Muto
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C8/12 , G11C16/16
摘要： An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.
摘要翻译：电可擦除半导体非易失性存储器件具有排列成行和列的存储单元阵列和一个或多个信息擦除信号发生电路。存储单元阵列的每个存储单元包括场效应晶体管元件，其具有与沿着行的方向延伸的字线导体连接的控制栅极，可以累积载流子的浮置栅极，与数据相连的漏极线导体沿列的方向延伸，源极与源极连接。存储单元阵列可以被划分为多个存储块，以便在行方向或列方向上具有沿着行方向或列方向布置的源极的边界。信息擦除信号可以以它们之间的时间延迟提供给源极导体或数据线导体。

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