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21. 发明授权

US08621156B1 Labeled cache system 有权
标题翻译：标记缓存系统
公开(公告)号：US08621156B1
公开(公告)日：2013-12-31
申请号：US13416109
申请日：2012-03-09
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F2212/1021 , G06F2212/502
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for labeled caching techniques. In one aspect, a method includes placing a plurality of items into a cache, each item having a label based on metadata associated with the item. A number of accesses are performed to respective items in the cache. A per-label stack distance histogram is determined for each label, including, for each label, determining a plurality of stack distances for accesses to items having the label. The cache is adjusted using the per-label stack distance histograms.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于标记的缓存技术。一方面，一种方法包括将多个项目放置在高速缓存中，每个项目具有基于与该项目相关联的元数据的标签。对高速缓存中的各个项目执行多个访问。对于每个标签确定每个标签堆栈距离直方图，包括对于每个标签，确定用于对具有该标签的物品的访问的多个堆叠距离。使用每标签堆栈距离直方图调整缓存。

22. 发明申请

US20060212775A1 System and method for tolerating communication lane failures 有权
标题翻译：用于容忍通信通道故障的系统和方法
公开(公告)号：US20060212775A1
公开(公告)日：2006-09-21
申请号：US11075478
申请日：2005-03-09
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H04L25/14 , H03M13/09 , H04L1/0045 , H04L1/0057 , H04L1/0063 , H04L1/18
摘要： A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of data may be conveyed to the receiver serially via respective single-bit lanes. The segment of data, the redundant information, and the error detecting code may be accumulated within the receiver over a plurality of clock cycles. The receiver may detect an error in the segment of data using the error detecting code. In addition, the receiver may, in response to detecting the error, regenerate the segment of data using the redundant information. Further, the receiver may determine whether a resulting regenerated bit, along with remaining bits, of the segment of data are correct using the error detecting code.
摘要翻译：用于容忍通信通道故障的系统包括被配置为发送数据段的发射机，错误检测码和冗余信息。该系统还包括经由包括多个位通道的通信链路耦合到发射机的接收机。数据段的每个位可以经由相应的单个位通道串行地传送到接收器。数据段，冗余信息和错误检测码可以在多个时钟周期内在接收器内累积。接收机可以使用错误检测码来检测数据段中的错误。此外，接收机可以响应于检测到错误，使用冗余信息再生数据段。此外，接收机可以使用错误检测码来确定所得到的再生位以及数据段的剩余位是否正确。

23. 发明申请

US20060083043A1 Memory system topology 有权
公开(公告)号：US20060083043A1
公开(公告)日：2006-04-20
申请号：US10989577
申请日：2004-11-16
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G11C5/02
CPC分类号： G06F13/4243 , G11C5/00
摘要： A memory subsystem. A memory subsystem includes a memory controller coupled to a processor and a plurality of N memory modules. The memory controller is directly coupled to convey information to the Nth memory module through a downstream link, and is directly coupled to receive information from a first memory module through an upstream link. Each of the memory modules may be coupled to a prior memory module via a downstream link. Information conveyed from the memory controller to a particular memory module is conveyed to the Nth memory module through the downstream link and, as necessary, through additional downstream links to the particular memory module. Each of the memory modules may be coupled to receive data from a subsequent memory module via an upstream link. Information conveyed from a memory module to the memory controller is conveyed from the memory module through upstream links to the memory controller.

24. 发明授权

US06477682B2 Technique for partitioning data to correct memory part failures 有权
标题翻译：分割数据以纠正内存部分故障的技术
公开(公告)号：US06477682B2
公开(公告)日：2002-11-05
申请号：US09854352
申请日：2001-05-10
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G11C2900
CPC分类号： G06F11/1028
摘要： The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.
摘要翻译：将数据块的比特分配给多个逻辑组，使得至多一个对应于分量的比特被分配给逻辑组。此分配确保组件故障最多可能向逻辑组引入一个位错误。选择逻辑组中的位数以减少给定数量的数据位的校验位的数量。可以在每个逻辑组内执行纠错，以纠正逻辑组中的单个错误。由于每个逻辑组最多分配一个与组件相对应的位，所以可以检测和校正组件故障。

25. 发明授权

US06453440B1 System and method for detecting double-bit errors and for correcting errors due to component failures 有权
标题翻译：用于检测双位错误并纠正由于组件故障引起的错误的系统和方法
公开(公告)号：US06453440B1
公开(公告)日：2002-09-17
申请号：US09368209
申请日：1999-08-04
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M1300
CPC分类号： G06F11/1024 , G06F11/1028
摘要： A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a pair of global error correction codes, referred to generally as an untwisted global error correction code and a twisted global error correction code. Data at corresponding bit positions within the logical groups are conveyed through a common component. The untwisted global error correction code may be equivalent to the result of generating an individual error correction code for each logical group and XORing the collection of individual error correction codes together. The twisted global error correction code may be equivalent to the result of (or may be derived by) shifting (either linearly or cyclically) the error correction code for a given ith group by i bit positions, wherein i=0 to X−1, and by XORing corresponding columns of the resulting shifted error correction codes together. An error correction unit is coupled to receive the plurality of data bits and the check bits following storage or transmission. The error correction unit is configured to generate a parity error bit for each of the logical groups of data based on the received data bits and the original parity bits, as well as first and second syndrome codes.
摘要翻译：用于检测和校正数据块中的错误的系统包括检验位产生单元，其接收并编码要被保护的数据。校验位生成单元有效地将数据分割成多个逻辑组。校验位生成单元为每个逻辑组生成奇偶校验位，并且另外生成一对全局纠错码，一般称为未扭绞全局纠错码和扭曲全局纠错码。在逻辑组中的相应位置处的数据通过公共组件传送。未经扭曲的全局纠错码可以等效于为每个逻辑组生成单独的纠错码并将各个纠错码的收集异或。扭曲的全局纠错码可以等同于（或可以通过）将给定的第i组的纠错码移动（或线性地或循环地）i比特位置的结果（或可以导出），其中i = 0到X-1，并将所得到的移位纠错码的相应列进行异或运算。耦合差错纠正单元以在存储或传输之后接收多个数据位和校验位。错误校正单元被配置为基于接收的数据位和原始奇偶校验位以及第一和第二校正码生成每个逻辑数据组的奇偶校验错误位。

26. 发明授权

US09148371B1 Configuring networks using balanced incomplete block designs 有权
标题翻译：使用平衡不完全块设计配置网络
公开(公告)号：US09148371B1
公开(公告)日：2015-09-29
申请号：US12981874
申请日：2010-12-30
申请人： Robert Cypher , Robert Ashby Armistead, III
发明人： Robert Cypher , Robert Ashby Armistead, III
IPC分类号： H04L12/28 , H04L12/775
CPC分类号： H04L45/583 , H04Q2213/1338
摘要： Methods for configuring networks and systems including nodes and switches. In one aspect, a method includes selecting a (v, b, r, k, λ) balanced incomplete block design (BIBD), wherein the BIBD includes v elements and b blocks of k elements, each element of the v elements is in r blocks of the b blocks, and each distinct pair of elements of the v elements is in λ blocks of the b blocks. Nodes are connected to switches. Each node is assigned to a different element of the BIBD. Each switch is assigned to a different block of the BIBD. For each switch, the switch is connected to the nodes assigned to the elements included in the block assigned to the switch.
摘要翻译：配置网络和系统的方法，包括节点和交换机。一方面，一种方法包括选择（v，b，r，k，λ）平衡不完全块设计（BIBD），其中BIBD包括k个元素的v个元素和b个块，v个元素的每个元素在r b块的块，并且v个元素的每个不同的元素对在b个块的λ个块中。节点连接到交换机。每个节点被分配给BIBD的不同元素。每个开关被分配到BIBD的不同块。对于每个交换机，交换机连接到分配给分配给交换机的块中包含的元素的节点。

27. 发明授权

US08713258B1 Estimating stack distances 有权
标题翻译：估计堆栈距离
公开(公告)号：US08713258B1
公开(公告)日：2014-04-29
申请号：US13233327
申请日：2011-09-15
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F12/08
CPC分类号： G06F12/0877
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for estimating the stack distance of an access to a cache. In one aspect, a method includes determining a current estimate value of the stack distance. For each of K buckets, a minimum value and a maximum value are initialized, wherein each bucket corresponds to a range of possible fingerprint values for accesses. A first access is processed, including: determining a first fingerprint value for the first access; identifying a first bucket for the first access based on the first fingerprint value; and determining that the first fingerprint value is between the minimum value and the maximum value for the first bucket, and in response, increasing the current estimate value and adjusting the minimum value or the maximum value for the first bucket.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于估计对高速缓存的访问的堆栈距离。一方面，一种方法包括确定堆栈距离的当前估计值。对于K个桶中的每一个，初始化最小值和最大值，其中每个桶对应于可能的访问指纹值的范围。处理第一访问，包括：确定第一访问的第一指纹值; 基于所述第一指纹值识别用于所述第一访问的第一桶; 并且确定第一指纹值在第一桶的最小值和最大值之间，并且作为响应，增加当前估计值并调整第一桶的最小值或最大值。

28. 发明申请

US20050228977A1 Branch prediction mechanism using multiple hash functions 审中-公开
标题翻译：使用多个散列函数的分支预测机制
公开(公告)号：US20050228977A1
公开(公告)日：2005-10-13
申请号：US10821431
申请日：2004-04-09
申请人： Robert Cypher , Stevan Vlaovic
发明人： Robert Cypher , Stevan Vlaovic
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3846 , G06F9/3848
摘要： In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second plurality of locations for storing a second set of partial prediction information. Further, the branch prediction mechanism includes a control unit that performs a first hash function on input branch information to generate a first index for accessing a selected location within the first storage. The control unit also performs a second hash function on the input branch information to generate a second index for accessing a selected location within the second storage. Lastly, the control unit further provides a prediction value based on corresponding partial prediction information in the selected locations of the first and the second storages.
摘要翻译：在一个实施例中，分支预测机制包括第一存储器，其包括用于存储第一组部分预测信息的第一多个位置。分支预测机制还包括包括用于存储第二组部分预测信息的第二多个位置的第二存储器。此外，分支预测机构包括：控制单元，其对输入的分支信息执行第一散列函数，以生成用于访问第一存储器内的选定位置的第一索引。控制单元还对输入的分支信息执行第二散列函数以产生用于访问第二存储器内的所选位置的第二索引。最后，控制单元进一步提供基于第一和第二存储器的选定位置中的相应部分预测信息的预测值。

29. 发明申请

US20050010615A1 Multi-node computer system implementing memory-correctable speculative proxy transactions 审中-公开
标题翻译：多节点计算机系统实现内存可纠正的投机代理事务
公开(公告)号：US20050010615A1
公开(公告)日：2005-01-13
申请号：US10821350
申请日：2004-04-09
申请人： Robert Cypher , Anders Landin
发明人： Robert Cypher , Anders Landin
IPC分类号： G06F17/30
CPC分类号： G06F12/0817 , G06F16/2308
摘要： A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network that communicates address packets between the devices. In response to receiving a coherency message that requests an access right to a coherency unit, the interface sends a proxy packet on the address network. In response to the proxy packet, the memory sends the interface data corresponding to the coherency unit and an indication of the global access state of the coherency unit within the node if the global access state is not the modified state. Otherwise, the memory sends an additional proxy packet on the address network. If the active device is the owner of the coherency unit, the active device ignores the proxy packet and responds to the additional proxy packet.
摘要翻译：节点包括若干设备，包括存储器，活动设备和被配置为在将节点耦合到另一节点的节点间网络上发送和接收一致性消息的接口以及在设备之间传送地址分组的地址网络。响应于接收到请求对一致性单元的访问权限的一致性消息，该接口在地址网络上发送代理分组。响应于代理分组，如果全局访问状态不是修改状态，则存储器发送对应于一致性单元的接口数据以及节点内的一致性单元的全局访问状态的指示。否则，内存会在地址网络上发送一个附加的代理数据包。如果活动设备是一致性单元的所有者，则活动设备忽略代理分组并响应附加代理分组。

30. 发明申请

US20050005075A1 Multi-node computer system employing multiple memory response states 审中-公开
标题翻译：采用多个存储器响应状态的多节点计算机系统
公开(公告)号：US20050005075A1
公开(公告)日：2005-01-06
申请号：US10821370
申请日：2004-04-09
申请人： Anders Landin , Robert Cypher , David Wood , Erik Hagersten , Mark Hill
发明人： Anders Landin , Robert Cypher , David Wood , Erik Hagersten , Mark Hill
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0817
摘要： A system may include a node and an additional node coupled by an inter-node network. The node may include an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device may send an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send data corresponding to the coherency unit to the active device dependent on memory response information associated with the coherency unit. If the transaction cannot be satisfied within the node, the memory is configured to forward a report corresponding to the address packet to the interface. In response to the report, the interface is configured to send the additional node a coherency message requesting the access right via the inter-node network.
摘要翻译：系统可以包括由节点间网络耦合的节点和附加节点。节点可以包括活动设备，到节点间网络的接口，存储器和耦合有源设备，接口和存储器的地址网络。活动设备可以发送地址分组以发起事务以获得对一致性单元的访问权限。响应于接收到地址分组，存储器被配置为根据与一致性单元相关联的存储器响应信息将对应于一致性单元的数据发送到活动设备。如果在节点内不能满足事务，则内存被配置为将与地址分组相对应的报告转发到接口。响应于该报告，该接口被配置为经由节点间网络向附加节点发送请求访问权限的一致性消息。

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