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21. 发明申请

US20110314186A1 Unified DMA 有权
标题翻译：统一DMA
公开(公告)号：US20110314186A1
公开(公告)日：2011-12-22
申请号：US13221622
申请日：2011-08-30
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

22. 发明申请

US20110307759A1 Functional DMA 审中-公开
标题翻译：功能DMA
公开(公告)号：US20110307759A1
公开(公告)日：2011-12-15
申请号：US13216411
申请日：2011-08-24
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Weichun Ku
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Weichun Ku
IPC分类号： G06F11/08 , G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。发送控制电路被配置为从主机中的地址空间读取第一DMA数据。耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

23. 发明授权

US08069279B2 Data flow control within and between DMA channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US08069279B2
公开(公告)日：2011-11-29
申请号：US11682051
申请日：2007-03-05
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F3/00 , G06F15/167
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

24. 发明授权

US07660931B2 System on a chip for networking 有权
标题翻译：系统在芯片上进行网络连接
公开(公告)号：US07660931B2
公开(公告)日：2010-02-09
申请号：US12178101
申请日：2008-07-23
申请人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
发明人： Mark D. Hayter , Joseph B. Rowlands , James Y. Cho
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

25. 发明授权

US07620746B2 Functional DMA performing operation on DMA data and writing result of operation 有权
标题翻译：功能DMA对DMA数据执行操作并写入操作结果
公开(公告)号：US07620746B2
公开(公告)日：2009-11-17
申请号：US11238850
申请日：2005-09-29
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Weichun Ku
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Weichun Ku
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。发送控制电路被配置为从主机中的地址空间读取第一DMA数据。耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

26. 发明授权

US07496695B2 Unified DMA 有权
标题翻译：统一DMA
公开(公告)号：US07496695B2
公开(公告)日：2009-02-24
申请号：US11238790
申请日：2005-09-29
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F3/00 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

27. 发明授权

US08566485B2 Data transformation during direct memory access 有权
标题翻译：直接内存访问期间的数据转换
公开(公告)号：US08566485B2
公开(公告)日：2013-10-22
申请号：US13566485
申请日：2012-08-03
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

28. 发明授权

US08458386B2 Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements 有权
标题翻译：中断控制器中的原子中断屏蔽，以防止传递相同的中断向量用于连续的中断确认
公开(公告)号：US08458386B2
公开(公告)日：2013-06-04
申请号：US12962089
申请日：2010-12-07
申请人： Michael J. Smith , Josh P. de Cesare , Mark D. Hayter
发明人： Michael J. Smith , Josh P. de Cesare , Mark D. Hayter
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812 , G06F9/52
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

29. 发明申请

US20120297096A1 Data Flow Control Within and Between DMA Channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US20120297096A1
公开(公告)日：2012-11-22
申请号：US13563127
申请日：2012-07-31
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

30. 发明授权

US08266338B2 Data flow control within and between DMA channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US08266338B2
公开(公告)日：2012-09-11
申请号：US13276537
申请日：2011-10-19
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

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