专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08592878B2 Semiconductor devices with low leakage Schottky contacts 有权
标题翻译：具有低泄漏肖特基接触的半导体器件
公开(公告)号：US08592878B2
公开(公告)日：2013-11-26
申请号：US13042948
申请日：2011-03-08
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L29/66
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译：实施例包括具有低泄漏肖特基接触的半导体器件。通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

22. 发明申请

US20090115001A1 MOS DEVICES WITH MULTI-LAYER GATE STACK 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US20090115001A1
公开(公告)日：2009-05-07
申请号：US12347061
申请日：2008-12-31
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/78
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
摘要翻译：半导体器件的实施例包括半导体衬底，其具有主表面，间隔开的源极和漏极区域，其在主表面处由沟道区域分隔开，并且多层栅极结构位于沟道区域上方。多层栅极结构包括与沟道区接触的栅极电介质层，包括覆盖栅极电介质层的金属氧化物的第一导体，覆盖第一导体的第二导体以及在栅极介电层和第二导体之间的杂质迁移抑制层第一导体或第一导体与第二导体之间。

23. 发明申请

US20110156051A1 SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS 有权
标题翻译：具有低漏电肖特基接触的半导体器件
公开(公告)号：US20110156051A1
公开(公告)日：2011-06-30
申请号：US13042948
申请日：2011-03-08
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L29/20 , H01L21/28 , H01L29/772
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译：实施例包括具有低泄漏肖特基接触的半导体器件。通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

24. 发明申请

US20090146191A1 LOW LEAKAGE SCHOTTKY CONTACT DEVICES AND METHOD 有权
标题翻译：低泄漏肖特基接触器件和方法
公开(公告)号：US20090146191A1
公开(公告)日：2009-06-11
申请号：US11950820
申请日：2007-12-05
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L29/00 , H01L21/338
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1). By minimizing the process steps between opening the Schottky contact window (35) in the passivation layer (25) and forming the Schottky contact (42-1) material in this window (35), the gate leakage of a resulting field effect device (51-5) having a Schottky gate (42-1) is substantially reduced.
摘要翻译：半导体器件描述了方法和装置。方法（100）包括提供包括衬底（21）的部分完成的半导体器件（31-1），在衬底（21）上的半导体（22）和半导体（22）上的钝化层（25）并且使用第一掩模（32）局部蚀刻钝化层（25）以暴露半导体（22）的一部分（36），并且不移除形成肖特基接触（42-1）的第一掩模（32）在所述半导体（22）的暴露部分（36）上的第一材料，然后去除所述第一掩模（32）并使用另外的掩模（44），形成第二材料的步进栅极导体（48-1）耦合到与肖特基触点（42-1）相邻的钝化层（25）的肖特基接触（42-1）和上覆部分（25-1）。通过最小化打开钝化层（25）中的肖特基接触窗（35）并在该窗口（35）中形成肖特基接触（42-1）材料之间的工艺步骤，得到的场效应器件（51）的栅极泄漏 -5）具有肖特基门（42-1）。

25. 发明授权

US07544576B2 Diffusion barrier for nickel silicides in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中硅化镍的扩散阻挡层
公开(公告)号：US07544576B2
公开(公告)日：2009-06-09
申请号：US11192968
申请日：2005-07-29
申请人： Dharmesh Jawarani , Chun-Li Liu , Marius K. Orlowski
发明人： Dharmesh Jawarani , Chun-Li Liu , Marius K. Orlowski
IPC分类号： H01L21/40
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4925 , H01L29/66636 , H01L29/7834
摘要： A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.
摘要翻译：半导体制造方法包括形成覆盖衬底的栅极模块。使用栅极模块作为掩模在衬底中蚀刻凹陷。阻挡层沉积在晶片上并进行各向异性蚀刻以在源极/漏极凹槽的侧壁上形成屏障“窗帘”。沉积金属层，其中金属层与凹部内的半导体接触。将晶片退火以选择性地形成硅化物。金属相对于阻挡结构材料的扩散率比金属相对于半导体材料的扩散率小一个数量级。蚀刻的凹槽可以包括再入口侧壁。金属层可以是镍层，阻挡层可以是氮化钛层。可以在覆盖半导体衬底的凹部中形成硅或硅锗外延结构。

26. 发明授权

US07510956B2 MOS device with multi-layer gate stack 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US07510956B2
公开(公告)日：2009-03-31
申请号：US11343623
申请日：2006-01-30
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L21/3205
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.
摘要翻译：为半导体器件提供了方法和装置。该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层，例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动杂质，例如氧气，朝向衬底。

27. 发明授权

US07238580B2 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US07238580B2
公开(公告)日：2007-07-03
申请号：US11043577
申请日：2005-01-26
申请人： Marius K. Orlowski , Vance H. Adams , Chun-Li Liu , Matthew W. Stoker
发明人： Marius K. Orlowski , Vance H. Adams , Chun-Li Liu , Matthew W. Stoker
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

28. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

29. 发明申请

US20060040433A1 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US20060040433A1
公开(公告)日：2006-02-23
申请号：US10919952
申请日：2004-08-17
申请人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

30. 发明申请

US20050070057A1 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US20050070057A1
公开(公告)日：2005-03-31
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
发明人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式