专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07340587B2 Information processing apparatus, microcomputer, and electronic computer 失效
标题翻译：信息处理装置，微电脑和电子计算机
公开(公告)号：US07340587B2
公开(公告)日：2008-03-04
申请号：US11149494
申请日：2005-06-09
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F9/24
CPC分类号： G06F9/3804
摘要： An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.
摘要翻译：执行流水线控制的信息处理装置包括获取非分支位置指令的第一提取提示，取得分支位置指令的第二提取提示，执行取出地址的算术的获取电路，将其提取到第一提取提示或第二提取提示，并且将第一提取提示或第二提取提示指令输出到解码电路;解码电路，其接收并解码获取到所述第一提取提示或所述第二提取提示的指令代码;执行电路，执行执行基于解码结果的指令，其中上述提取电路包括选择电路，其基于比较指令的执行结果来选择要向解码电路发送的第一提取提示或第二提取提示的哪个指令。

22. 发明授权

US07223993B2 Optical semiconductor device 有权
标题翻译：光半导体器件
公开(公告)号：US07223993B2
公开(公告)日：2007-05-29
申请号：US11210760
申请日：2005-08-25
申请人： Kouji Nakahara , Makoto Kudo , Shigehisa Tanaka , Masataka Shirai
发明人： Kouji Nakahara , Makoto Kudo , Shigehisa Tanaka , Masataka Shirai
IPC分类号： H01L29/06
CPC分类号： H01S5/34313 , B82Y20/00 , G02F1/01708 , G02F2001/01766 , H01S5/0265 , H01S5/0287 , H01S5/12 , H01S5/1221 , H01S5/227 , H01S5/305 , H01S5/3054 , H01S5/3406 , H01S5/34306 , H01S5/34366 , Y10S438/962
摘要： In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ΔEc and ΔEv, have been unable to be adjusted independently.This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.
摘要翻译：在包括应变量子阱层作为有源层的半导体激光器或电吸收光学调制器中，由于带结构，特别是DeltaEc和DeltaEv已经不能独立地调整，所以使激光特性或调制器特性足够的已经看到相应的限制。本发明通过将n型InGaAlAs-GRIN-SCH层3，MQW层4，p型InGaAlAs-GRIN-SCH层5，p型InAlAs电子停止层6等层叠而构成在n型InP晶片1上的顺序; 其中MQW层4包括InGaAlAs应变的量子阱层和InGaAlAsSb形成的阻挡层，每个具有与施加到量子阱层的应变相反的符号的应变。

23. 发明申请

US20050278515A1 Information processing apparatus, microcomputer, and electronic computer 失效
标题翻译：信息处理装置，微电脑和电子计算机
公开(公告)号：US20050278515A1
公开(公告)日：2005-12-15
申请号：US11149494
申请日：2005-06-09
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3804
摘要： An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.
摘要翻译：执行流水线控制的信息处理装置包括获取非分支位置指令的第一提取提示，取得分支位置指令的第二提取提示，执行取出地址的算术的获取电路，将其提取到第一提取提示或第二提取提示，并且将第一提取提示或第二提取提示指令输出到解码电路;解码电路，其接收并解码获取到所述第一提取提示或所述第二提取提示的指令代码;执行电路，执行执行基于解码结果的指令，其中上述提取电路包括选择电路，其基于比较指令的执行结果来选择要向解码电路发送的第一提取提示或第二提取提示的哪个指令。

24. 发明授权

US06885255B2 Clock control system using converting clock control sections to provide a minimum clock number to operate corresponding devices 有权
标题翻译：时钟控制系统使用转换时钟控制部分来提供操作相应设备的最小时钟数
公开(公告)号：US06885255B2
公开(公告)日：2005-04-26
申请号：US10372119
申请日：2003-02-25
申请人： Makoto Kudo , Keisuke Hashimoto
发明人： Makoto Kudo , Keisuke Hashimoto
IPC分类号： G06F1/04 , G06F1/08 , G06F1/10 , H03B1/00
CPC分类号： G06F1/08
摘要： The invention saves power by supplying minimum clocks required for respective blocks. In a clock control system that supplies clocks to a plurality of blocks, such as a CPU-4, a bus, a peripheral circuit and other circuits, a clock supplied from a clock oscillator is supplied to clock control sections that are connected to the blocks, respectively. The clock is converted by the clock control sections into clocks with minimum clock numbers required to operate the blocks, respectively, and supplied to the blocks.
摘要翻译：本发明通过提供相应块所需的最小时钟来节省功率。在诸如CPU-4，总线，外围电路等电路向多个块提供时钟的时钟控制系统中，从时钟振荡器提供的时钟提供给连接到块的时钟控制部分，分别。时钟由时钟控制部分转换为分别操作块所需的最小时钟数的时钟，并提供给块。

25. 发明授权

US06782032B2 Semiconductor laser, ray module using the same and ray communication system 有权
标题翻译：半导体激光器，射线模块使用相同的和射线通信系统
公开(公告)号：US06782032B2
公开(公告)日：2004-08-24
申请号：US10154822
申请日：2002-05-28
申请人： Masahiko Kondow , Takeshi Kitatani , Makoto Kudo
发明人： Masahiko Kondow , Takeshi Kitatani , Makoto Kudo
IPC分类号： H01S319
CPC分类号： H01S5/18308 , B82Y20/00 , H01S5/02284 , H01S5/0421 , H01S5/06226 , H01S5/18311 , H01S5/18341 , H01S5/18358 , H01S5/18369 , H01S5/3054 , H01S5/32366 , H01S5/34306 , H01S2301/166
摘要： In a semiconductor laser for emitting light perpendicular to substrate crystal, including, on the substrate crystal, an active layer for generating light, a cavity structure sandwiching the active layer by reflecting mirrors so as to obtain a laser beam from the light generated from the active layer, and a regrown semiconductor layer between the active layer and one of the reflecting mirrors, a regrown interface or a face very close to the regrown interface is formed by a thin film containing dopants of high concentration. With the configuration, an adverse influence of a contamination deposit on the regrown interface is eliminated by delta-doping the regrown interface. The cost is reduced and device resistance is also reduced to 50 &OHgr; or less. Thus, an edge emitting laser (VCSEL) for realizing a optical module achieving a high speed characteristic over 10 Gb/s is obtained.
摘要翻译：在用于发射与衬底晶体垂直的光的半导体激光器中，在衬底晶体上包括用于产生光的有源层，通过反射镜夹持有源层的空腔结构，以便从活性物质产生的光获得激光束层和在有源层和一个反射镜之间的再生长半导体层，通过含有高浓度掺杂剂的薄膜形成非常接近再生界面的再生长界面或面。通过配置，通过对再生界面的δ掺杂，消除了污染沉积物对再生界面的不利影响。成本降低，器件电阻也降低到50欧姆以下。因此，获得用于实现10Gb / s以上的高速特性的光模块的边缘发射激光器（VCSEL）。

26. 发明授权

US06570149B2 Photodetector having a control block for maintaining a detection signal within a predetermined tolerance range 失效
标题翻译：光检测器具有用于将检测信号保持在预定公差范围内的控制块
公开(公告)号：US06570149B2
公开(公告)日：2003-05-27
申请号：US09812682
申请日：2001-03-21
申请人： Tomoyuki Maruyama , Makoto Kudo , Fumio Narusawa
发明人： Tomoyuki Maruyama , Makoto Kudo , Fumio Narusawa
IPC分类号： H01J4014
CPC分类号： H01L31/02027 , H01L31/024
摘要： There is disclosed a photodetector which is capable of attaining an enhanced detection accuracy, and at the same time permits reduction in the size and manufacturing costs thereof. An avalanche photodiode detects an incident light, in a state of a predetermined bias voltage set thereto. A cooler cools the avalanche photodiode to a predetermined cooling temperature. An amount of an incident signal light incident on the avalanche photodiode is detected based on a detection signal from the avalanche photodiode. A control block adjusts at least one of the bias voltage and the predetermined cooling temperature, thereby holding a value of the detection signal from the avalanche photodiode generated in a state of the incident light being blocked from impinging on the avalanche photodiode, within a predetermined tolerance range.
摘要翻译：公开了一种能够提高检测精度的光电检测器，同时可以减小其尺寸和制造成本。雪崩光电二极管以预定的偏置电压的状态检测入射光。冷却器将雪崩光电二极管冷却至预定的冷却温度。基于来自雪崩光电二极管的检测信号检测入射在雪崩光电二极管上的入射信号光的量。控制块调整偏置电压和预定冷却温度中的至少一个，从而保持来自在入射光的状态下产生的雪崩光电二极管的检测信号的值在预定的公差内被阻挡以撞击在雪崩光电二极管上范围。

27. 发明申请

US20090235052A1 Data Processing Device and Electronic Equipment 审中-公开
标题翻译：数据处理设备和电子设备
公开(公告)号：US20090235052A1
公开(公告)日：2009-09-17
申请号：US12417505
申请日：2009-04-02
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/325 , G06F9/3842
摘要： A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.
摘要翻译：使用流水线架构提供数据处理装置，以减少由于分支引起的时间损失而不引起电路规模的增加。数据处理设备使用流水线控制。数据处理装置包括可以取出多个指令代码的指令队列，计算取出地址的取出地址运算电路，基于取出地址取出指令代码的取出电路以及分支信息设定电路解码分支设置指令，将分支地址存储在分支地址存储寄存器中，并将分支目标地址存储在分支目标地址存储寄存器中。提取地址操作电路将先前的取出地址或预期的下一个取出地址与存储在分支地址存储寄存器中的值进行比较，并且基于比较结果确定要输出的下一个提取地址。

28. 发明授权

US07340589B2 Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction 失效
标题翻译：移位前缀指令解码器，用于修改解码目标指令所需的寄存器信息
公开(公告)号：US07340589B2
公开(公告)日：2008-03-04
申请号：US10601136
申请日：2003-06-20
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/30196 , G06F9/3842
摘要： The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a decode processing only on a prefix instruction. The prefix instruction decoder circuit receives the instruction code before decoding, judges whether or not the instruction is a given prefix instruction, and causes a target instruction to modify an information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction. A decoder circuit receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction. When the decode instruction is a target instruction, the target instruction modified by the prefix instruction is decoded based on the target instruction modifying information.
摘要翻译：本发明的数据处理装置和电子设备执行流水线控制，并且包括取指令电路，其取指令队列中的多个指令的指令代码。前缀指令解码器电路只对前缀指令进行解码处理。前缀指令译码器电路在解码之前接收指令码，判断指令是否是给定的前缀指令，并且当指令是给定的前缀时，使目标指令修改信息寄存器以存储解码目标指令所需的信息指令。解码器电路接收除了前缀指令之外的指令的指令代码作为解码指令，并对解码指令进行解码。当解码指令是目标指令时，由前缀指令修改的目标指令基于目标指令修改信息进行解码。

29. 发明申请

US20060218378A1 Integrated circuit device 审中-公开
标题翻译：集成电路器件
公开(公告)号：US20060218378A1
公开(公告)日：2006-09-28
申请号：US11389458
申请日：2006-03-24
申请人： Makoto Kudo
发明人： Makoto Kudo
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/321 , G06F9/322 , G06F9/3853 , G06F9/3877
摘要： An integrated circuit device including: a CPU which executes given processing based on an instruction code; an instruction code bus used to supply an instruction code to the CPU from a memory; and an instruction code supply line used to supply an instruction code output from a coprocessor to the CPU. The CPU includes: a fetch section which fetches an instruction code; and an instruction code select circuit which receives an instruction code input through the instruction code bus and an instruction code supplied through the instruction code supply line, and supplies one of the instruction codes to the fetch section.
摘要翻译：一种集成电路装置，包括：执行基于指令代码的给定处理的CPU; 用于从存储器向CPU提供指令代码的指令代码总线; 以及用于将从协处理器输出的指令代码提供给CPU的指令代码供给线。 CPU包括：提取部分，其获取指令代码; 以及指令代码选择电路，其接收通过指令代码总线输入的指令代码和通过指令代码提供线提供的指令代码，并将指令代码中的一个提供给获取部分。

30. 发明申请

US20050086454A1 System and methods for providing a debug function built-in type microcomputer 审中-公开
标题翻译：用于提供调试功能的系统和方法内置型微型计算机
公开(公告)号：US20050086454A1
公开(公告)日：2005-04-21
申请号：US10377762
申请日：2003-03-04
申请人： Toshihiko Morigaki , Makoto Kudo
发明人： Toshihiko Morigaki , Makoto Kudo
IPC分类号： G06F11/28 , G06F9/00 , G06F11/22 , G06F11/36 , G06F12/10 , G06F15/00 , G06F15/78
CPC分类号： G06F11/364
摘要： The present invention provides a debug function built-in type microcomputer that is capable of restricting outputs only to necessary information to prevent necessary information from being terminated halfway and performing a more accurate tracing in real time, when an output signal line having a bit width fewer than a bit width of an inner bus is used for tracing information on the inner bus. The debug function built-in type microcomputer can be provided with registers that temporarily store bus information prepared for each target bus to be traced, a register writing condition judgment circuit that controls temporary storage of the bus information in the registers according to a trace condition stored in a setting register, and a multiplexer that selects and outputs the bus information temporarily stored in the registers.
摘要翻译：本发明提供了一种调试功能内置型微计算机，其能够将输出仅限于必要的信息，以防止必要的信息被中途终止，并且当具有位宽较少的输出信号线时，实时执行更准确的跟踪内部总线的位宽度用于跟踪内部总线上的信息。调试功能内置型微型计算机可以设置有临时存储为要跟踪的每个目标总线准备的总线信息的寄存器，根据存储的跟踪条件控制寄存器中的总线信息的暂时存储的寄存器写入条件判断电路在设置寄存器中，以及多路复用器，其选择并输出临时存储在寄存器中的总线信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式