专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

CA2107906A1 ZINC OXIDE VARISTOR AND PROCESS FOR THE PRODUCTION THEREOF 未知
公开(公告)号：CA2107906A1
公开(公告)日：1993-08-26
申请号：CA2107906
申请日：1993-02-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOYAMA KAZUSHIGE , MUTOH NAOKI , KATSUMATA MASAAKI
IPC分类号： H01C7/112 , H01C7/10

22. 发明专利

GB2437465B Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board 未知
公开(公告)号：GB2437465B
公开(公告)日：2010-11-17
申请号：GB0714966
申请日：2006-02-01
申请人： MATSUSHITA ELECTRIC IND CO LTD , PANASONIC CORP
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITOU YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K1/18 , H01L23/31 , H01L23/498
摘要： A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.

23. 发明专利

DE60210445D1 未知
公开(公告)号：DE60210445D1
公开(公告)日：2006-05-18
申请号：DE60210445
申请日：2002-05-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASHIMOTO AKIRA , NAKAO KEIICHI , KATSUMATA MASAAKI
IPC分类号： H05K3/46 , C04B37/00 , H01L21/48 , H01L23/15 , H05K1/03 , H05K1/09 , H05K3/38

24. 发明专利

DE69027867D1 未知
公开(公告)号：DE69027867D1
公开(公告)日：1996-08-22
申请号：DE69027867
申请日：1990-11-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KATSUMATA MASAAKI , KANAYA OSAMU , KATSUKI NOBUHARU , TAKAMI AKIHIRO
IPC分类号： H01C7/102 , H01C7/112 , H01C7/10
摘要： A zinc oxide varistor comprises a sintered body (1), the side surfaces of which are coated by a high-resistance layer (2). The major component of (1) is zinc oxide. (1) has itself varistor characteristics. (2) is composed of a crystallised glass contg., as major component, SiO2 (6.0-15.0 wt.%). The high resistance layer of the side surfaces comprises PbO (50.0-75.0 wt.%), ZnO (10.0-30.0 wt.%), B2O3 (5.0-10.0 wt.%) and SiO2 (6.0-15.0 wt.%). This compsn. is the crystallised glass coating compsn. The zinc oxide varistor is produced by coating a glass plate contg. the above-mentioned crystallised glass and an organic cpd. on the side surfaces of the sintered body (10.0-150.0 mg/cm2 thick) and heating at 450-650 deg.C. The linear expansion coefft. of the crystallised glass is 65 x 10 power (-7) to 90 x 10 power (-7)/deg.C. The high resistance layer coated on the side surfaces of the sintered body can be PbO contg. molybdenum oxide (0.1-10.0 wt.% calculated as the MoO3) or a PbO-ZnO-B2O3-MoO3 system crystallised glass having the compsn.: PbO (50.0-75.0 wt.%), ZnO (10.0-30.0 wt.%), B2O3 (5.0-15.0 wt.%), SiO2 (0-15.0 wt.%) and MoO3 (0.1-10.0 wt.%).

25. 发明专利

JP2006216755A Multilayer wiring board, its manufacturing method, semiconductor device using the same, and electronic equipment 有权
标题翻译：多层接线板及其制造方法，使用其的半导体器件和电子设备
公开(公告)号：JP2006216755A
公开(公告)日：2006-08-17
申请号：JP2005027569
申请日：2005-02-03
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , ASAHI TOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI , SAITO YOSHIYUKI , NAKAYAMA TAKESHI
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H05K1/186 , H01L23/3128 , H01L23/49822 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H05K3/429 , H05K3/4623 , H05K2201/09536 , H05K2201/10015 , Y10T29/4913 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To enable many bypass capacitors mounted on a mother board to be built as sheet-shaped capacitors in the interposer board of a semiconductor package so as to make semiconductors operate stably, and to provide a device in which a reduction of components can be achieved. SOLUTION: The board is provided which is composed of a multilayer wiring board containing, at least, two wiring layers; a solid-state electrolytic capacitor which is formed between the wiring layers of the multilayer wiring board, and consists of an insulating oxide film layer, an electrolytic layer, and a conductor layer successively formed on one or both of the sides of a foil-like metal base; and a conductive member which is provided through the multilayer board in its thickness direction, wherein the conductor layer is connected to the ground electrode of the multilayer wiring board, and the foil-like metal base is connected to the power supply layer electrode of the multilayer wiring board. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了使得安装在母板上的许多旁路电容器被构建为半导体封装的插入板中的片状电容器，以使半导体稳定地工作，并且提供一种器件，其中可以实现部件的减少。解决方案：提供由包含至少两个布线层的多层布线板组成的板; 固体电解电容器，其形成在多层布线板的布线层之间，并且由绝缘氧化物膜层，电解质层和导体层构成，所述绝缘氧化物膜层，电解质层和导体层依次形成在箔状的一个或两侧上金属底座; 以及导电构件，其通过所述多层板在其厚度方向上设置，其中所述导体层连接到所述多层布线板的接地电极，并且所述箔状金属基底连接到所述多层布线基板的所述电源层电极接线板版权所有（C）2006，JPO＆NCIPI

26. 发明专利

JP2005276981A Method of manufacturing module with built-in circuit component 审中-公开
标题翻译：使用内置电路组件制造模块的方法
公开(公告)号：JP2005276981A
公开(公告)日：2005-10-06
申请号：JP2004086243
申请日：2004-03-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHITOMI HIROYUKI , KATSUMATA MASAAKI , KAWAMOTO EIJI
IPC分类号： H05K9/00 , H01L23/12 , H05K3/46
CPC分类号： H01L24/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a module with built-in circuit components which can easily accomplish a shielding effect good enough for reduction in size, height, and weight of an electronic apparatus which is responsive to higher frequency by improving the shielding property of the module with built-in circuit components. SOLUTION: In manufacturing the module with built-in circuit components, a plate member 20 formed with through-holes 21 and a releasing film 25 mounted with circuit components 24 are laminated to form an electric insulation substrate 26. The electric insulation substrate 26 is cut into single circuit boards. Then, on the front surface and cut faces of an insulating resin of each single circuit board 31 divided by cutting, a first metal layer 28 is formed by electroless copper plating, a second metal layer 29 is formed by electrolytic copper plating, and a third metal layer 30 for preventing the oxidation of copper is formed by metal plating. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造具有内置电路部件的模块的方法，其可以容易地实现足够的屏蔽效果，以减小响应于较高频率的电子设备的尺寸，高度和重量通过提高内置电路元件的模块的屏蔽性能。解决方案：在制造具有内置电路元件的模块时，层叠形成有通孔21的板构件20和安装有电路部件24的剥离膜25，以形成电绝缘基板26.电绝缘基板 26被切成单电路板。然后，在通过切割分割的每个单电路板31的绝缘树脂的前表面和切割面上，通过无电镀铜形成第一金属层28，通过电解铜电镀形成第二金属层29，通过金属电镀形成用于防止铜的氧化的金属层30。版权所有（C）2006，JPO＆NCIPI

27. 发明专利

JP2005175044A Method of mounting electronic component 审中-公开
标题翻译：安装电子元件的方法
公开(公告)号：JP2005175044A
公开(公告)日：2005-06-30
申请号：JP2003410018
申请日：2003-12-09
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NIIMI HIDEKI , KASHIWAGI TAKAFUMI , HASHIMOTO AKIRA , KATSUMATA MASAAKI
IPC分类号： H05K3/32 , H01L21/60 , H05K3/34
CPC分类号： H01L2224/16 , H01L2924/19105
摘要： PROBLEM TO BE SOLVED: To provide a method of mounting components which makes it possible to mount a semiconductor component and electronic components close to each other when mounting the semiconductor component and electronic components on a circuit board in a mixed state, and hence enables high-density mixed mounting of the components.
SOLUTION: Before mounting the semiconductor component 2, solder paste 12 is applied on the circuit board 1. Then, after mounting the semiconductor component 2, the electronic components 9 and 10 are mounted on the circuit board 1. By this method, when printing the solder paste 12 on the circuit board 1, there is no need to go around the semiconductor component 2, and the solder paste 12 can be printed close to a portion where the semiconductor component 2 is mounted. Consequently, the semiconductor component 2 and the electronic components 9 and 10 can be mounted close to each other, resulting in enabling high-density mixed mounting of the components.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种安装部件的方法，当将半导体部件和电子部件以混合状态安装在电路板上时，可以将半导体部件和电子部件安装在彼此靠近，因此实现了组件的高密度混合安装。解决方案：在安装半导体部件2之前，将焊膏12施加在电路板1上。然后，在安装半导体部件2之后，将电子部件9和10安装在电路板1上。通过该方法，当在电路板1上印刷焊膏12时，不需要绕着半导体部件2，并且可以将焊膏12印刷到靠近半导体部件2安装部分的位置。因此，半导体组件2和电子部件9和10可以彼此靠近地安装，从而能够实现组件的高密度混合安装。版权所有（C）2005，JPO＆NCIPI

28. 发明专利

JP2005159227A Circuit component contained module, and method for manufacturing the same 审中-公开
标题翻译：电路组件包含模块及其制造方法
公开(公告)号：JP2005159227A
公开(公告)日：2005-06-16
申请号：JP2003399059
申请日：2003-11-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHITOMI HIROYUKI , KATSUMATA MASAAKI , KAWAMOTO EIJI , HAYAMA MASAAKI
IPC分类号： H05K9/00 , H05K1/02 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a circuit component contained module wherein an electromagnetic-field shield layer can be formed simply without using any metal cover, and environmental assessment is also considered.
SOLUTION: The circuit component contained module has a circuit component 104 composed of one or more electronic components and has a wiring board 102 having electrodes 103 for mounting the circuit component on its surface layer and having one or more wiring layers. Further, in the module, the circuit component 104 and the electrodes 103 of the wiring board 102 are connected with solder or a conductive adhesives 105, and these are covered with an insulating resin 107. Moreover, conductive foil 114 is so formed on the surface layer of the insulating resin 107, and the conductive foil 114 and grounding patterns 111 of the wiring board 102 are so connected electrically by using conductive substances 115 as to form an electromagnetic-field shield layer in the module.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种包含电路元件的模块，其中可以简单地形成电磁屏蔽层而不使用任何金属盖，并且还考虑环境评估。解决方案：包含电路部件的模块具有由一个或多个电子部件组成的电路部件104，并且具有布线板102，该布线板102具有电极103，用于将电路部件安装在其表面层上并具有一个或多个布线层。此外，在该模块中，电路部件104和布线基板102的电极103与焊料或导电性粘合剂105连接，并且被绝缘树脂107覆盖。此外，导体箔114形成在表面绝缘树脂107的层，导电箔114和布线板102的接地图案111通过使用导电物质115电连接以在模块中形成电磁场屏蔽层。版权所有（C）2005，JPO＆NCIPI

29. 发明专利

JP2005159076A Solder packaging method of electronic part 审中-公开
标题翻译：电子部件的焊接包装方法
公开(公告)号：JP2005159076A
公开(公告)日：2005-06-16
申请号：JP2003396885
申请日：2003-11-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HASHIMOTO AKIRA , NIIMI HIDEKI , KASHIWAGI TAKAFUMI , KATSUMATA MASAAKI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a solder packaging method for electronic parts by which a chip or a flip chip can be packaged by printing a solder pattern on the land of a circuit board and high density packaging can be easily attained.
SOLUTION: The solder packaging method consists of a process for packaging a semiconductor flip chip 12 on a circuit board 11, a process for forming a solder pattern 18 on a transfer base material 17, a process for transferring the solder pattern 18 to a solder packaging land 16 on the circuit board 11, a process for sticking and temporarily fixing a semiconductor packaging part such as a chip 20 on the solder pattern 18 transferred to the solder packaging land 16 on the circuit board 11, and a process for heating the circuit board 11 on which the solder packaging part is stuck and temporarily fixed and connecting the solder packaging part to the circuit board 11 by melting solder to a melted state. Consequently, the solder pattern 18 of a narrow pitch can be formed and high density packaging can be attained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种用于电子部件的焊料包装方法，通过其可以通过在电路板的焊盘上印刷焊料图案来封装芯片或倒装芯片，并且可以容易地获得高密度封装。焊料包装方法包括在电路板11上封装半导体倒装芯片12的工艺，在转印基材17上形成焊料图案18的工艺，将焊料图案18转印到电路板11上的焊料包装用焊盘16，将转印到电路基板11上的焊料包装用焊盘16上的焊料图案18上贴附并临时固定芯片20等半导体封装部的工序，以及加热工序焊接包装部分被卡住并临时固定的电路板11，并且通过将焊料熔化成熔融状态将焊料包装部分连接到电路板11。因此，可以形成窄间距的焊料图案18，并且可以实现高密度封装。版权所有（C）2005，JPO＆NCIPI

30. 发明专利

JP2000216005A MANUFACTURE OF ZINC OXIDE VARISTOR 失效
公开(公告)号：JP2000216005A
公开(公告)日：2000-08-04
申请号：JP1181199
申请日：1999-01-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYAUCHI KATSUYUKI , KATSUMATA MASAAKI
IPC分类号： H01C7/10
摘要： PROBLEM TO BE SOLVED: To provide a zinc oxide varistor having uniform thickness and a high resistance layer. SOLUTION: High resistance layer forming material is applied to the side face of a cylindrical calcined body containing the main component of zinc oxide and the subsidiary component of bithmuth oxide, cobalt oxide, nickel oxide and silicon oxide, etc., and while said calcined body is being rotated, a uniformly thick high resistance layer forming material is applied to the side face of the cylindrical calcined body. Then, said calcined body is sintered, and a sintered body 1, having a high resistance layer 2 on the side face, is obtained. Then, an electrode 3 is formed on the upper and the lower surfaces of the sintered body.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式