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21. 发明申请

US20100287436A1 System for Error Decoding with Retries and Associated Methods 有权
标题翻译：使用重试和关联方法进行错误解码的系统
公开(公告)号：US20100287436A1
公开(公告)日：2010-11-11
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winogard
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winogard
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译：通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于队列中的数据包。

22. 发明申请

US20100281202A1 WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES 有权
标题翻译：有限寿命内存设备的磨损和边框管理
公开(公告)号：US20100281202A1
公开(公告)日：2010-11-04
申请号：US12433220
申请日：2009-04-30
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/00 , G06F11/20 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C29/76 , G11C29/82
摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
摘要翻译：执行有限寿命内存设备的磨损均衡和坏块管理。用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。使用代数映射将中间地址映射到存储器的物理地址。物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。输出物理地址用于访问存储器。中间地址和物理地址之间的映射周期性地移位。此外，坏块的内容被替换为冗余编码的重定向地址。

23. 发明申请

US20090006886A1 SYSTEM AND METHOD FOR ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于记忆系统中错误校正和检测的系统和方法
公开(公告)号：US20090006886A1
公开(公告)日：2009-01-01
申请号：US11769929
申请日：2007-06-28
申请人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/20
CPC分类号： G06F11/108 , G06F2211/1045 , G06F2211/1057 , G06F2211/1064
摘要： A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.
摘要翻译：一种用于存储系统中的纠错和检测的系统和方法。该系统包括存储器控制器，多个存储器模块和机构。存储器模块与存储器控制器和多个存储器件通信。该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。

24. 发明申请

US20080163032A1 SYSTEMS AND METHODS FOR ERROR DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于记忆系统中错误检测的系统和方法
公开(公告)号：US20080163032A1
公开(公告)日：2008-07-03
申请号：US11619015
申请日：2007-01-02
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , G06F11/1044 , H03M13/159 , H03M13/3715
摘要： A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then the calculated signatures are compared to one or more signatures in a trapping set. The trapping set includes signatures associated with uncorrectable errors. An uncorrectable error flag is set in response to determining that at least one of the calculated signatures is equal to a signature in the trapping set.
摘要翻译：一种存储系统中的错误检测方法。该方法包括计算与包含错误的数据相关联的一个或多个签名。确定错误是否是潜在的可纠正错误。如果错误是潜在的可纠正错误，则将计算的签名与陷阱集中的一个或多个签名进行比较。陷阱集包括与不可纠正错误相关联的签名。响应于确定所计算的签名中的至少一个等于捕获集合中的签名，设置不可校正的错误标志。

25. 发明授权

US08897062B2 Memory programming for a phase change memory cell 有权
标题翻译：相变存储单元的存储器编程
公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G11C13/00 , G11C29/02
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

26. 发明授权

US08488397B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08488397B2
公开(公告)日：2013-07-16
申请号：US13557298
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.
摘要翻译：在异构存储元件中提供增加的容量，包括从存储器读取的方法。该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。读取的字被分成两个或更多个虚拟读取向量。对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。生成包括将虚拟读取向量乘以代表码本的矩阵。将部分读取数据矢量组合成读取消息，并输出读出的消息。

27. 发明授权

US08463985B2 Constrained coding to reduce floating gate coupling in non-volatile memories 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US08463985B2
公开(公告)日：2013-06-11
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , H03M13/00
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

28. 发明授权

US08374040B2 Write bandwidth in a memory characterized by a variable write time 有权
标题翻译：将带宽写入以可变写入时间为特征的存储器中
公开(公告)号：US08374040B2
公开(公告)日：2013-02-12
申请号：US13034936
申请日：2011-02-25
申请人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
发明人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： G11C7/00
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译：一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

29. 发明申请

US20130013886A1 ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM 有权
标题翻译：通过监测记忆参考流的性质，自适应磨损
公开(公告)号：US20130013886A1
公开(公告)日：2013-01-10
申请号：US13619513
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/1052 , G06F2212/7201 , G06F2212/7211
摘要： Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.
摘要翻译：在有限寿命的存储器设备中的自适应写平均化，包括执行用于监视包括写入行地址的写入数据流的方法。检测写入数据流的属性，并响应于检测到的属性来调整写入调平过程。写入平均过程被应用于写入数据流以从写入地址生成物理地址。

30. 发明申请

US20130013860A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20130013860A1
公开(公告)日：2013-01-10
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

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