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21. 发明授权

US08999863B2 Stress liner for stress engineering 有权
标题翻译：应力工程应力衬
公开(公告)号：US08999863B2
公开(公告)日：2015-04-07
申请号：US12133375
申请日：2008-06-05
申请人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
发明人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
摘要翻译：具有第一和第二应力类型的应力衬垫设置在第一类型和第二类型晶体管上，以提高可靠性和性能，而不会引起区域损失或布局缺陷。

22. 发明授权

US08957470B2 Integration of memory, high voltage and logic devices 有权
标题翻译：内存，高电压和逻辑器件的集成
公开(公告)号：US08957470B2
公开(公告)日：2015-02-17
申请号：US13526550
申请日：2012-06-19
申请人： Yan Zhe Tang , Shyue Seng Tan , Ying Keung Leung , Elgin Quek
发明人： Yan Zhe Tang , Shyue Seng Tan , Ying Keung Leung , Elgin Quek
IPC分类号： H01L29/788
CPC分类号： H01L21/82385 , H01L21/76224 , H01L21/823857 , H01L21/823892 , H01L27/0928 , H01L27/11546
摘要： A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.
摘要翻译：公开了一种用于形成装置的装置和方法。该装置包括具有第一，第二和第三区域的基板。第一区域包括存储单元区域，第二区域包括外围电路区域，第三区域包括逻辑区域。包括具有第一堆叠高度（TSM）的存储晶体管的存储单元设置在第一区域中。具有第二叠层高度（TSHV）的高压（HV）晶体管设置在第二区域中，并且具有第三叠层高度（TSL）的逻辑晶体管设置在第三区域中。第一，第二和第三堆叠高度在基板上基本相同。

23. 发明授权

US08698118B2 Compact RRAM device and methods of making same 有权
标题翻译：紧凑的RRAM设备及其制作方法
公开(公告)号：US08698118B2
公开(公告)日：2014-04-15
申请号：US13408221
申请日：2012-02-29
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04 , H01L29/06
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
摘要翻译：这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间的至少一个可变电阻材料层。

24. 发明授权

US08674332B2 RRAM device with an embedded selector structure and methods of making same 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制作方法
公开(公告)号：US08674332B2
公开(公告)日：2014-03-18
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

25. 发明申请

US20140008713A1 METHOD AND APPARATUS FOR EMBEDDED NVM UTILIZING AN RMG PROCESS 有权
标题翻译：用于嵌入式NVM的方法和装置利用RMG过程
公开(公告)号：US20140008713A1
公开(公告)日：2014-01-09
申请号：US13543340
申请日：2012-07-06
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/8239 , H01L27/088
CPC分类号： H01L21/823437 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L27/11524 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
摘要翻译：通过集成嵌入式非易失性存储器（eNVM）与RMG进程来制造存储器件。实施例包括在衬底的上表面上形成第一和第二双多晶硅栅叠层结构，在第一和第二双多晶硅栅叠层结构中的每一个的相对侧壁上形成间隔物，形成与露出侧壁相邻的ILD 移除所述第一双多晶硅栅堆叠结构，在所述间隔物之间形成第一空腔，并在所述第一空腔中形成HKMG，其中所述HKMG形成存取栅极。

26. 发明申请

US20130270501A1 RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制造方法
公开(公告)号：US20130270501A1
公开(公告)日：2013-10-17
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

27. 发明申请

US20130240821A1 THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME 有权
标题翻译：三维RRAM装置及其制造方法
公开(公告)号：US20130240821A1
公开(公告)日：2013-09-19
申请号：US13423793
申请日：2012-03-19
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2409 , H01L27/2445 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.
摘要翻译：本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极线和第二位线的可变电阻材料。

28. 发明授权

US08368127B2 Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current 有权
标题翻译：制造具有高驱动电流的硅隧道场效应晶体管（TFET）的方法
公开(公告)号：US08368127B2
公开(公告)日：2013-02-05
申请号：US12587511
申请日：2009-10-08
申请人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , B82Y10/00 , H01L29/0895 , H01L29/7391 , H01L29/7606 , H01L29/7613
摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
摘要翻译：制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

29. 发明申请

US20120112256A1 Control gate structure and method of forming a control gate structure 审中-公开
标题翻译：控制门结构和形成控制栅结构的方法
公开(公告)号：US20120112256A1
公开(公告)日：2012-05-10
申请号：US12925991
申请日：2010-11-04
申请人： Shyue Seng Tan , Ying Keung Leung , Elgin Quek
发明人： Shyue Seng Tan , Ying Keung Leung , Elgin Quek
IPC分类号： H01L29/68 , H01L21/71
CPC分类号： H01L29/42332 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions.
摘要翻译：提供半导体器件和制造器件的方法。示例性器件可以包括衬底和衬底上的栅极结构。栅极结构包括具有至少三个不同栅极区域的控制栅极。第一和第二控制栅极区被配置为第一场类型，例如高栅极或低栅极型。配置为第二场类型（不同于第一场类型）的第三控制栅极区域至少部分地设置在第一和第二控制栅极区域之间。

30. 发明授权

US08993407B2 Compact localized RRAM cell structure realized by spacer technology 有权
标题翻译：通过间隔技术实现紧凑的局部RRAM单元结构
公开(公告)号：US08993407B2
公开(公告)日：2015-03-31
申请号：US13683779
申请日：2012-11-21
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.
摘要翻译：公开了一种具有垂直BJT选择器的RRAM。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

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