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21. 发明授权

US07241696B2 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer 失效
标题翻译：在具有覆盖层的半导体互连结构上沉积金属层的方法
公开(公告)号：US07241696B2
公开(公告)日：2007-07-10
申请号：US10318606
申请日：2002-12-11
申请人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
发明人： Larry Clevenger , Timothy Joseph Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik Kumar , Douglas C. La Tulipe, Jr. , Soon-Cheon Seo , Andrew Herbert Simon , Yun-Yu Wang , Chih-Chao Yang , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
摘要翻译：公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。在该方法中，金属导体被覆盖层和电介质层覆盖。对电介质层进行图案化以使覆盖层露出。然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

22. 发明授权

US07060619B2 Reduction of the shear stress in copper via's in organic interlayer dielectric material 有权
标题翻译：在有机层间介质材料中减少铜通道中的剪切应力
公开(公告)号：US07060619B2
公开(公告)日：2006-06-13
申请号：US10379346
申请日：2003-03-04
申请人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要翻译：形成包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层以显着减少相邻导体/通孔之间的短路数量的方式形成， 0.18微米或更小。这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。较厚的阻挡层消除了对覆盖层的需要。消除覆盖层导致整体电容耦合，应力和成本的降低。

23. 发明授权

US07001835B2 Crystallographic modification of hard mask properties 失效
标题翻译：硬掩模性能的晶体学修饰
公开(公告)号：US07001835B2
公开(公告)日：2006-02-21
申请号：US10707119
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/4763
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/0332 , H01L21/0337 , H01L21/2855 , H01L21/76841 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.
摘要翻译：集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和通过硬掩模和ILD的中间层降低对准标记。形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

24. 发明申请

US20050077628A1 Dual damascene structure and method 有权
公开(公告)号：US20050077628A1
公开(公告)日：2005-04-14
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

25. 发明授权

US5989633A Process for overcoming CVD aluminum selectivity loss with warm PVD aluminum 失效
标题翻译：使用温热PVD铝克服CVD铝选择性损失的工艺
公开(公告)号：US5989633A
公开(公告)日：1999-11-23
申请号：US638762
申请日：1996-04-29
申请人： Mark Hoinkis
发明人： Mark Hoinkis
IPC分类号： C23C14/14 , C23C14/16 , C23C16/04 , C23C16/20 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/768 , C23C16/06
CPC分类号： C23C16/045 , C23C14/16 , C23C16/20 , H01L21/7684
摘要： The present invention provides a process for depositing a planarized metal film on a dielectric surface having nonuniform conductor material deposits formed thereon. The planarized metal layer is formed using a warm physical vapor deposition process at a temperature greater than about 150.degree. C., preferably greater than about 250.degree. C. The nonuniform deposits of electrically conducting material are typically formed during selective chemical vapor deposition of a metal in high aspect ratio, subhalf micron apertures. The selective CVD deposition is directly followed by warm physical vapor deposition to obtain a planarized metal film. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form interconnects occurs without the formation of oxides between the layers.
摘要翻译：本发明提供了在其上形成有不均匀的导体材料沉积物的电介质表面上沉积平坦化金属膜的方法。在大于约150℃，优选大于约250℃的温度下使用热物理气相沉积工艺形成平坦化金属层。导电材料的不均匀沉积物通常在金属的选择性化学气相沉积期间形成在高纵横比，亚微米微孔。直接进行选择性CVD沉积，然后进行热物理气相沉积以获得平坦化的金属膜。金属化工艺优选在包括PVD和CVD处理室的集成处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成互连，而不会在层之间形成氧化物。

26. 发明授权

US07786007B2 Method and apparatus of stress relief in semiconductor structures 有权
标题翻译：半导体结构中应力消除的方法和装置
公开(公告)号：US07786007B2
公开(公告)日：2010-08-31
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

27. 发明申请

US20080213993A1 Method and Apparatus of Stress Relief in Semiconductor Structures 有权
标题翻译：半导体结构应力消除的方法与装置
公开(公告)号：US20080213993A1
公开(公告)日：2008-09-04
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

28. 发明申请

US20050093159A1 Stress-relief layer for semiconductor applications 有权
标题翻译：用于半导体应用的应力消除层
公开(公告)号：US20050093159A1
公开(公告)日：2005-05-05
申请号：US10698057
申请日：2003-10-30
申请人： Hans-Joachim Barth , Erdem Kaltalioglu , Mark Hoinkis , Gerald Friese , Pak Leung
发明人： Hans-Joachim Barth , Erdem Kaltalioglu , Mark Hoinkis , Gerald Friese , Pak Leung
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.
摘要翻译：在半导体集成电路器件中，可以通过在通孔和覆盖在通孔之间的硬电介质层之间引入应力消除层来减小通孔上的热机械应力。

29. 发明授权

US06539625B2 Chromium adhesion layer for copper vias in low-k technology 失效
公开(公告)号：US06539625B2
公开(公告)日：2003-04-01
申请号：US09759017
申请日：2001-01-11
申请人： Brett H. Engel , Mark Hoinkis , John A. Miller , Soon-Cheon Seo , Yun-Yu Wang , Kwong Hon Wong
发明人： Brett H. Engel , Mark Hoinkis , John A. Miller , Soon-Cheon Seo , Yun-Yu Wang , Kwong Hon Wong
IPC分类号： H05K302
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Cr, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while maintaining low resistance.

30. 发明授权

US06383929B1 Copper vias in low-k technology 失效
标题翻译：铜通孔在低k技术
公开(公告)号：US06383929B1
公开(公告)日：2002-05-07
申请号：US09759015
申请日：2001-01-11
申请人： Steven H. Boettcher , Herbert L. Ho , Mark Hoinkis , Hyun Koo Lee , Yun-Yu Wang , Kwong Hon Wong
发明人： Steven H. Boettcher , Herbert L. Ho , Mark Hoinkis , Hyun Koo Lee , Yun-Yu Wang , Kwong Hon Wong
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76858 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
摘要翻译：在具有铜互连和低k层间电介质的集成电路中，通过使用第一内衬层Ti，随后是CVD TiN的共形内衬层，然后依次由 Ta或TaN的最终衬垫层，从而改善了通孔和下面的铜层之间的粘附性，同时将Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

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