专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20060280867A1 Apparatus and method for depositing tungsten nitride 审中-公开
标题翻译：氮化钨沉积设备和方法
公开(公告)号：US20060280867A1
公开(公告)日：2006-12-14
申请号：US11361087
申请日：2006-02-22
申请人： Jin-Ho Park , Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee
发明人： Jin-Ho Park , Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee
IPC分类号： C23C16/00
CPC分类号： C23C16/34 , C23C16/4408 , C23C16/45561
摘要： An apparatus for depositing a thin film on a substrate includes a processing chamber, supply pipes, and discharge pipes. Each supply pipe is configured to supply a process gas to the processing chamber, and each discharge pipe is connected to one of the supply pipes and an inhale part configured to discharge gas remaining inside the one of the supply pipes. Each of the discharge pipes is separate from one another.
摘要翻译：用于在基板上沉积薄膜的设备包括处理室，供应管和排出管。每个供给管被构造成将处理气体供给到处理室，并且每个排出管连接到供应管中的一个和被配置为排出剩余在供给管内的气体的吸入部。每个排放管彼此分开。

22. 发明授权

US07300887B2 Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers 失效
标题翻译：形成金属氮化物层的方法，以及形成具有金属氮化物层的半导体结构的方法
公开(公告)号：US07300887B2
公开(公告)日：2007-11-27
申请号：US11227542
申请日：2005-09-15
申请人： Jae-Hwa Park , Kwang-Jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jeong-Tae Kim , Jang-Hee Lee
发明人： Jae-Hwa Park , Kwang-Jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jeong-Tae Kim , Jang-Hee Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/28556 , H01L21/76843 , H01L21/76849 , H01L21/76862 , H01L28/60
摘要： Methods of forming metal nitride layers on a substrate include reacting a metal source gas with a nitrogen source gas in a process chamber to form a metal nitride layer on the substrate. The process chamber may have an atmosphere having a pressure of about 0.1 mTorr to about 5 mTorr and a temperature of about 200° C. to about 450° C. A ratio of the flow rate of the metal source gas to the flow rate of the nitrogen source gas may be “1” or more. An interlayer insulating layer may be formed on the semiconductor substrate prior to formation of the metal nitride layer. Some methods include forming a contact hole in the interlayer insulating layer to expose a portion of the semiconductor substrate prior to forming the metal nitride layer
摘要翻译：在基板上形成金属氮化物层的方法包括在处理室中使金属源气体与氮源气体反应，以在衬底上形成金属氮化物层。处理室可以具有约0.1mTorr至约5mTorr的压力和约200℃至约450℃的温度的气氛。金属源气体的流量与流动速率的比率氮源气体可以为“1”以上。在形成金属氮化物层之前，可以在半导体衬底上形成层间绝缘层。一些方法包括在层间绝缘层中形成接触孔，以在形成金属氮化物层之前露出半导体衬底的一部分

23. 发明申请

US20060246710A1 Methods of fabricating semiconductor devices including contact plugs having laterally extending portions and related devices 有权
标题翻译：制造半导体器件的方法，包括具有横向延伸部分的接触插塞和相关器件
公开(公告)号：US20060246710A1
公开(公告)日：2006-11-02
申请号：US11409685
申请日：2006-04-24
申请人： Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Jin-Ho Park
发明人： Seong-Hwee Cheong , Gil-Heyun Choi , Sang-Woo Lee , Jin-Ho Park
IPC分类号： H01L21/4763 , H01L21/76
CPC分类号： H01L27/1108 , H01L21/28562 , H01L21/76802 , H01L21/76843 , H01L21/76846 , H01L27/0688 , H01L27/11
摘要： In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.
摘要翻译：在形成集成电路器件的方法中，形成延伸穿过第一和第二绝缘层并且穿过其间的半导体层到基板表面的开口。开口包括在与半导体层相邻的第一和第二绝缘层之间的侧壁中的凹部。导电插塞形成在开口的侧壁和基板的表面上，并横向延伸到第一和第二绝缘层之间的凹部中以接触半导体层。可以在侧壁处选择性地蚀刻半导体层，而不必在开口的侧壁基本上蚀刻第一和第二绝缘层，以在第一和第二绝缘层之间形成凹部。还讨论了相关设备。

24. 发明申请

US20060115984A1 Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers 失效
标题翻译：形成金属氮化物层的方法，以及形成具有金属氮化物层的半导体结构的方法
公开(公告)号：US20060115984A1
公开(公告)日：2006-06-01
申请号：US11227542
申请日：2005-09-15
申请人： Jae-Hwa Park , Kwang-Jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jeong-Tae Kim , Jang-Hee Lee
发明人： Jae-Hwa Park , Kwang-Jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jeong-Tae Kim , Jang-Hee Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28556 , H01L21/76843 , H01L21/76849 , H01L21/76862 , H01L28/60
摘要： Methods of forming metal nitride layers on a substrate include reacting a metal source gas with a nitrogen source gas in a process chamber to form a metal nitride layer on the substrate. The process chamber may have an atmosphere having a pressure of about 0.1 mTorr to about 5 mTorr and a temperature of about 200° C. to about 450° C. A ratio of the flow rate of the metal source gas to the flow rate of the nitrogen source gas may be “1” or more. An interlayer insulating layer may be formed on the semiconductor substrate prior to formation of the metal nitride layer. Some methods include forming a contact hole in the interlayer insulating layer to expose a portion of the semiconductor substrate prior to forming the metal nitride layer
摘要翻译：在基板上形成金属氮化物层的方法包括在处理室中使金属源气体与氮源气体反应，以在衬底上形成金属氮化物层。处理室可以具有约0.1mTorr至约5mTorr的压力和约200℃至约450℃的温度的气氛。金属源气体的流量与流动速率的比率氮源气体可以为“1”以上。在形成金属氮化物层之前，可以在半导体衬底上形成层间绝缘层。一些方法包括在层间绝缘层中形成接触孔，以在形成金属氮化物层之前露出半导体衬底的一部分

25. 发明申请

US20120012969A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120012969A1
公开(公告)日：2012-01-19
申请号：US13240599
申请日：2011-09-22
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L27/108
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

26. 发明授权

US08030204B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08030204B2
公开(公告)日：2011-10-04
申请号：US12217932
申请日：2008-07-10
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

27. 发明申请

US20090035941A1 METHODS AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A PROCESSING CHAMBER 审中-公开
标题翻译：在加工室中制造半导体器件的方法和装置
公开(公告)号：US20090035941A1
公开(公告)日：2009-02-05
申请号：US12183421
申请日：2008-07-31
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Jun-Ho Park , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Jun-Ho Park , Ho-Ki Lee
IPC分类号： C23C16/00 , H01L21/44
CPC分类号： H01L21/28562 , C23C16/06 , C23C16/34 , C23C16/45519 , C23C16/54 , H01L21/6719 , H01L21/67207 , H01L21/76843 , H01L21/76846 , H01L21/76856
摘要： An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit.
摘要翻译：一种用于制造半导体器件的设备包括：处理室，被配置为在衬底上执行多个不同的处理。气体供应单元被配置为向处理室供应至少一种处理气体。至少一个上电极单元位于处理室的上部。至少一个下电极单元与上电极单元相对，并且构造成在其上支撑基板。驱动构件连接到下电极单元和上电极单元中的至少一个，并且被配置为移动下电极单元和/或上电极单元以控制上电极单元和下电极单元之间的距离。电源单元被配置为向所述上电极单元施加第一电力并且向所述下电极单元施加第二电力。

28. 发明授权

US08466556B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08466556B2
公开(公告)日：2013-06-18
申请号：US13240599
申请日：2011-09-22
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L29/40
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

29. 发明授权

US07547607B2 Methods of fabricating integrated circuit capacitors using a dry etching process 失效
标题翻译：使用干蚀刻工艺制造集成电路电容器的方法
公开(公告)号：US07547607B2
公开(公告)日：2009-06-16
申请号：US11176519
申请日：2005-07-07
申请人： Kwang-jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jae-Hwa Park
发明人： Kwang-jin Moon , Gil-Heyun Choi , Sang-Woo Lee , Jae-Hwa Park
IPC分类号： H01L21/20
CPC分类号： H01L21/76889 , H01L21/28518 , H01L21/32137 , H01L27/10852 , H01L28/91 , H01L28/92
摘要： A method of fabricating an integrated circuit capacitor includes forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate. At least a portion of the first metal layer is silicided to form a metal silicide layer and a remaining first metal layer on the conductive plug. The remaining first metal layer is removed using a dry etching process. A lower electrode including a second metal layer is then formed on the metal silicide layer. Because the remaining first metal layer is removed, etching and/or other damage to the conductive plug and/or the interlayer insulating layer during a subsequent wet ethching process may be reduced and/or prevented.
摘要翻译：制造集成电路电容器的方法包括在基板上的层间绝缘层中的导电插塞上形成第一金属层。第一金属层的至少一部分被硅化以在导电插塞上形成金属硅化物层和剩余的第一金属层。使用干蚀刻工艺除去剩余的第一金属层。然后在金属硅化物层上形成包括第二金属层的下电极。因为剩余的第一金属层被去除，所以可以减少和/或阻止在随后的湿式加工过程中对导电塞和/或层间绝缘层的蚀刻和/或其它损坏。

30. 发明申请

US20090014879A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090014879A1
公开(公告)日：2009-01-15
申请号：US12217932
申请日：2008-07-10
申请人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
发明人： Jin-Ho Park , Gil-Heyun Choi , Sang-Woo Lee , Ho-Ki Lee
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/485 , H01L21/28562 , H01L21/76846 , H01L21/76865 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
摘要翻译：在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式