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21. 发明申请

US20050259480A1 Method and apparatus for providing debug functionality in a buffered memory channel 有权
标题翻译：用于在缓冲存储器通道中提供调试功能的方法和装置
公开(公告)号：US20050259480A1
公开(公告)日：2005-11-24
申请号：US11192249
申请日：2005-07-27
申请人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , David Zimmerman
发明人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , David Zimmerman
IPC分类号： G11C5/00 , G11C29/48 , G11C29/56
CPC分类号： G11C29/48 , G11C29/56 , G11C2029/5602
摘要： Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
摘要翻译：本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。在权利要求中描述了其它实施例。

22. 发明授权

US08321778B2 Efficient in-band reliability with separate cyclic redundancy code frames 有权
标题翻译：具有独立循环冗余码帧的高效带内可靠性
公开(公告)号：US08321778B2
公开(公告)日：2012-11-27
申请号：US12139610
申请日：2008-06-16
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/1004
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for efficient in-band reliability with separate cyclic redundancy code (CRC) frames. In some embodiments, a memory system uses data frames to transfer data between a host and a memory device. The system also uses a separate frame (e.g., a CRC frame) to transfer a CRC checksum that covers the data frames.
摘要翻译：本发明的实施例一般涉及用于利用单独的循环冗余码（CRC）帧来有效地进行带内可靠性的系统，方法和装置。在一些实施例中，存储器系统使用数据帧来在主机和存储设备之间传送数据。该系统还使用单独的帧（例如，CRC帧）来传送覆盖数据帧的CRC校验和。

23. 发明申请

US20070150667A1 Multiported memory with ports mapped to bank sets 审中-公开
标题翻译：多端口存储器，端口映射到银行集
公开(公告)号：US20070150667A1
公开(公告)日：2007-06-28
申请号：US11317757
申请日：2005-12-23
申请人： Kuljit Bains , John Halbert , Randy Osborne
发明人： Kuljit Bains , John Halbert , Randy Osborne
IPC分类号： G06F13/28
CPC分类号： G06F13/1684
摘要： In some embodiments, a chip includes first and second bank sets, a first data port mapped to the first bank set, and a second data port mapped to the second bank set. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括第一和第二组组，映射到第一组组的第一数据端口和映射到第二组组的第二数据端口。描述其他实施例。

24. 发明申请

US20070008328A1 Identifying and accessing individual memory devices in a memory channel 有权
标题翻译：识别和访问存储器通道中的各个存储器件
公开(公告)号：US20070008328A1
公开(公告)日：2007-01-11
申请号：US11174236
申请日：2005-07-05
申请人： Peter MacWilliams , James Akiyama , Kuljit Bains , Douglas Gabel
发明人： Peter MacWilliams , James Akiyama , Kuljit Bains , Douglas Gabel
IPC分类号： G06T1/60
CPC分类号： G06F12/0646
摘要： In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
摘要翻译：在本发明的一个实施例中，提供了存储器集成电路，其包括存储器阵列，寄存器和耦合到寄存器的控制逻辑。存储器集成电路中的存储器阵列存储数据。寄存器包括一个或多个位存储电路以存储一个或多个标识值的同一位。响应于存储在寄存器中的一个或多个同步位，控制逻辑提供对存储器集成电路的独立子通道存储器访问。

25. 发明申请

US20060106951A1 Command controlling different operations in different chips 有权
标题翻译：命令控制不同芯片的不同操作
公开(公告)号：US20060106951A1
公开(公告)日：2006-05-18
申请号：US10992953
申请日：2004-11-18
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F3/00
CPC分类号： G06F13/4086 , G11C5/04
摘要： In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the first command to cause the chip to perform a first operation if the operation type signal has a first value and to cause the chip to perform a second operation if the operation type signal has a second value. The chip may be a memory chip in a memory system. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括具有包括操作类型信号的寄存器的芯片。该芯片还包括用于接收第一命令的控制电路，并且响应于第一命令使芯片执行第一操作，如果操作类型信号具有第一值并使芯片执行第二操作，如果操作类型信号具有第二个值。芯片可以是存储器系统中的存储器芯片。描述和要求保护其他实施例。

26. 发明申请

US20050146975A1 Method and apparatus for multiple row caches per bank 有权
标题翻译：每行多行缓存的方法和装置
公开(公告)号：US20050146975A1
公开(公告)日：2005-07-07
申请号：US10750038
申请日：2003-12-30
申请人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
发明人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
IPC分类号： G11C7/10 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C11/4096 , G11C2207/005
摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.
摘要翻译：提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问内容通过读取操作使至少一行直接从存储器单元行读取数据从读出放大器行读取。

27. 发明申请

US20050081085A1 Memory buffer device integrating ECC 有权
标题翻译：集成ECC的内存缓冲设备
公开(公告)号：US20050081085A1
公开(公告)日：2005-04-14
申请号：US10674320
申请日：2003-09-29
申请人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert
发明人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1044
摘要： Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译：在存储器总线上没有活动的情况下，与存储器控制器独立地对存储器件内的存储器错误执行检查的装置和方法，该存储器总线将存储器装置耦合到涉及存储器件的存储器控制器。

28. 发明授权

US09117544B2 Row hammer refresh command 有权
标题翻译：行锤刷新命令
公开(公告)号：US09117544B2
公开(公告)日：2015-08-25
申请号：US14068677
申请日：2013-10-31
申请人： Kuljit Bains , John Halbert , Christopher Mozak , Theodore Schoenborn , Zvika Greenfield
发明人： Kuljit Bains , John Halbert , Christopher Mozak , Theodore Schoenborn , Zvika Greenfield
IPC分类号： G06F13/10 , G11C11/406 , G11C7/02
CPC分类号： G11C11/40615 , G11C7/02 , G11C11/40611 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
摘要翻译：内存控制器发出目标刷新命令。存储器件的特定行可以是重复访问的目标。当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

29. 发明申请

US20090327792A1 BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：总线频率调整电路用于动态随机访问存储器件
公开(公告)号：US20090327792A1
公开(公告)日：2009-12-31
申请号：US12163663
申请日：2008-06-27
申请人： Joe Salmon , Kuljit Bains
发明人： Joe Salmon , Kuljit Bains
IPC分类号： G06F1/06
CPC分类号： G06F1/10 , G06F1/06
摘要： The present disclosure relates to clock divider circuitry for use in a dynamic random access memory device. In accordance with at least one embodiment the disclosure includes a method having a number of operations. Some operations may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving said clock input signal and said output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving said multiplexed output at a first bus configured to receive said multiplexed output and to reduce an operational frequency of said first bus in response to an increase in an operational frequency of a second bus associated with said memory device.
摘要翻译：本公开涉及用于动态随机存取存储器件的时钟分配器电路。根据至少一个实施例，本公开包括具有多个操作的方法。一些操作可以包括在时钟分频器电路处从时钟输入接收器接收具有第一频率的时钟输入信号，时钟分频器电路包括被配置为产生输出信号的触发器，至少部分地基于反相输出信号和时钟输入信号。输出信号可以具有第二频率，其是第一频率的一部分。该方法还可以包括在多路复用器处接收所述时钟输入信号和所述输出信号，并产生多路复用输出。该方法可以另外包括在被配置为接收所述多路复用输出的第一总线处接收所述多路复用输出并且响应于与所述存储器件相关联的第二总线的工作频率的增加而减小所述第一总线的工作频率。

30. 发明申请

US20070121399A1 Semiconductor memory devices and systems, and methods of using having reduced timers and registers 有权
标题翻译：半导体存储器件和系统以及使用方法具有减少的定时器和寄存器
公开(公告)号：US20070121399A1
公开(公告)日：2007-05-31
申请号：US11291285
申请日：2005-11-30
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22
摘要： A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued, and control logic coupled to the command decoder to precharge bit lines no earlier than when the timer reaches a target time period.
摘要翻译：一种装置，包括用于接收复合命令的命令解码器，如果所述复合命令包括激活命令和预充电命令，定时器开始运行，所述定时器开始在与所述激活命令相同的时间开始操作，以及控制逻辑耦合到命令解码器，以便在定时器达到目标时间段之前不对其进行预充电。

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