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    • 22. 发明授权
    • Fault containment and error recovery in a scalable multiprocessor
    • 可扩展多处理器中的故障控制和错误恢复
    • US06678840B1
    • 2004-01-13
    • US09651949
    • 2000-08-31
    • Richard E. KesslerPeter J. BannonKourosh GharachorlooThukalan V. Verghese
    • Richard E. KesslerPeter J. BannonKourosh GharachorlooThukalan V. Verghese
    • G06F1100
    • G06F11/0793G06F11/0724G06F15/17
    • A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    • 多处理器计算机系统允许实现各种类型的分区以包含和隔离硬件故障。 各种类型的分区包括硬,半硬,坚固和软分区。 每个分区可以包括一个或多个处理器。 当检测到与处理器相关联的故障时,可以切断与系统中的相邻处理器的连接,从而防止损坏的数据污染系统的其余部分。 如果处理器间连接被切断,则在其他处理器中的消息备份时,系统中的消息流量可能会变得拥塞。 因此,每个处理器包括各种定时器,以监视可能由于切断的连接造成的交通拥堵。 而不是让处理器继续等待能够发送其消息,定时器将在预编程的时间段过期,并且处理器将采取适当的动作,例如简单地删除排队的消息,以防止系统锁定。
    • 23. 发明授权
    • Detecting anomalies
    • 检测异常
    • US07523016B1
    • 2009-04-21
    • US11618607
    • 2006-12-29
    • Razvan SurdulescuKourosh Gharachorloo
    • Razvan SurdulescuKourosh Gharachorloo
    • G06F11/30G21C17/00
    • H04L63/1416G06F21/316G06F21/552G06Q30/00H04L63/1425
    • In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically derived measures of how extreme the cell is relative to, for example, historical behavior of corresponding characteristics or relative to, for example, behavior of characteristics from a general population. Cells that have more than a predefined number of such annotations can be identified as anomalous and can be investigated by a user or outright acted upon in an automatic, pre-defined way.
    • 一般来说,描述用于识别异常活动的系统和方法。 例如,描述了系统和方法,其中可以通过将记录的或采样的数据聚合到单元中并且通过统计学上导出的测量来注释每个单元来识别该异常行为的模式,该度量对于诸如历史行为 或相对于例如来自普通人群的特征的行为。 具有超过预定数量的这种注释的单元可以被识别为异常的,并且可以由用户进行调查或直接以自动的,预定义的方式进行操作。
    • 27. 发明授权
    • Fault containment and error recovery in a scalable multiprocessor
    • 可扩展多处理器中的故障控制和错误恢复
    • US07152191B2
    • 2006-12-19
    • US10691744
    • 2003-10-23
    • Richard E. KesslerPeter J. BannonKourosh GharachorlooThukalan V. Verghese
    • Richard E. KesslerPeter J. BannonKourosh GharachorlooThukalan V. Verghese
    • G06F11/00
    • G06F11/0793G06F11/0724G06F15/17
    • A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    • 多处理器计算机系统允许实现各种类型的分区以包含和隔离硬件故障。 各种类型的分区包括硬,半硬,坚固和软分区。 每个分区可以包括一个或多个处理器。 当检测到与处理器相关联的故障时,可以切断与系统中的相邻处理器的连接,从而防止损坏的数据污染系统的其余部分。 如果处理器间连接被切断,则在其他处理器中的消息备份时,系统中的消息流量可能会变得拥塞。 因此,每个处理器包括各种定时器,以监视可能由于切断的连接造成的交通拥堵。 而不是让处理器继续等待能够发送其消息,定时器将在预编程的时间段过期,并且处理器将采取适当的动作,例如简单地删除排队的消息,以防止系统锁定。
    • 28. 发明授权
    • Scalable directory based cache coherence protocol
    • 基于可扩展目录的缓存一致性协议
    • US06633960B1
    • 2003-10-14
    • US09652703
    • 2000-08-31
    • Richard E. KesslerKourosh GharachorlooDavid H. Asher
    • Richard E. KesslerKourosh GharachorlooDavid H. Asher
    • G06F1200
    • G06F12/0817G06F12/0828
    • A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block. Eviction of a memory block copy held by an Owner processor in its cache requires a write of the memory block copy to its Home and update of the corresponding coherence directory. No reads of the Home processor directory or modification of other processor cache and main memory is required. The coherence controller in each processor is able to send and receive messages out of order to maintain the coherence of the shared data in cache and main memory. If an out of order message causes an incorrect next program state, the coherence controller is able to restore the prior correct saved program state and resume execution.
    • 公开了一种维护多处理计算机系统的节点中包含的高速缓存和存储器中的共享数据的一致性的系统和方法。 分布式多处理计算机系统包含多个处理器,每个处理器连接到主存储器。 分布式多处理计算机系统中的处理器被识别为用于存储器块的家庭处理器,如果其包括原始存储器块和用于其主存储器中的存储器块的一致性目录。 所有者处理器是多处理计算机系统中的另一个处理器,其包括连接到其主存储器的高速缓存中的家庭处理器存储器块的副本。 无论何时存在一个内存块的所有者处理器,它是分布式多处理计算机系统中唯一包含家庭处理器内存块副本的处理器。 驱逐由所有者处理器在其高速缓存中保存的存储器块副本需要将存储器块副本写入其归属并更新相应的一致性目录。 不需要读取家庭处理器目录或修改其他处理器缓存和主内存。 每个处理器中的相干控制器能够发送和接收消息,以保持缓存和主存储器中的共享数据的一致性。 如果故障信息导致不正确的下一个程序状态,则相干控制器能够恢复先前正确保存的程序状态并恢复执行。