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    • 22. 发明授权
    • Nonvolatile semiconductor device
    • 非易失性半导体器件
    • US06806532B2
    • 2004-10-19
    • US09908848
    • 2001-07-20
    • Kiyoteru Kobayashi
    • Kiyoteru Kobayashi
    • H01L29792
    • H01L27/11568H01L29/66833
    • A nonvolatile semiconductor memory device is formed in which data in the form of electrons trapped in the silicon layers directly on the source and the drain respectively can hardly be lost or replaced with other data. The semiconductor device has a memory transistor includes a drain and a source, an insulating layer, and a gate electrode. The drain and the source are formed in an upper region of a semiconductor substrate. The insulating layer, which has an area interrupting the electron migration arranged in a particular region thereof between the drain and the source for interrupting the electron migration, is formed between the drain and the source. In addition, the gate electrode is formed on the insulating layer.
    • 形成非易失性半导体存储器件,其中分别直接在源极和漏极上的陷阱在硅层中的电子形式的数据难以丢失或被其它数据替代。 半导体器件具有包括漏极和源极,绝缘层和栅电极的存储晶体管。 漏极和源极形成在半导体衬底的上部区域中。 在漏极和源极之间形成绝缘层,其具有中断在漏极和源极之间的特定区域中的电子迁移的区域以中断电子迁移。 此外,栅电极形成在绝缘层上。
    • 23. 发明授权
    • Non-volatile semiconductor memory device with improved performance
    • 具有改进性能的非易失性半导体存储器件
    • US06710395B2
    • 2004-03-23
    • US10166264
    • 2002-06-11
    • Kiyoteru KobayashiOsamu Sakamoto
    • Kiyoteru KobayashiOsamu Sakamoto
    • H01L29788
    • H01L27/11521H01L27/115
    • The non-volatile semiconductor memory device includes: a semiconductor substrate having a main surface; N+ diffusion layers formed spaced from each other at the main surface of the semiconductor substrate; a floating gate formed on a region between the N+ diffusion layers with a silicon oxide film interposed; an access gate formed adjacent to the floating gate on the region between N+ diffusion layers with a silicon oxide film interposed; and a control gate formed on the floating gate with an interlayer insulating film interposed. The N+ diffusion layer is provided between the floating gates, and another N+ diffusion layer is provided between the access gates. Thus performance of a memory transistor in a non-volatile semiconductor memory device is improved, reliability of the device is improved and miniaturization of the device is facilitated.
    • 非易失性半导体存储器件包括:具有主表面的半导体衬底; N + +扩散层在半导体衬底的主表面彼此隔开形成; 形成在N +扩散层之间的区域上的氧化硅膜的浮置栅极; 在N +扩散层之间的区域上与浮置栅极相邻形成的存取栅,其间插有氧化硅膜; 以及在所述浮置栅极上形成有夹层绝缘膜的控制栅极。 N +扩散层设置在浮置栅极之间,另外N +扩散层设置在栅极之间。 因此,提高了非易失性半导体存储器件中的存储晶体管的性能,改善了器件的可靠性并且便于器件的小型化。
    • 24. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 非易失性半导体器件
    • US06501125B2
    • 2002-12-31
    • US09504588
    • 2000-02-15
    • Kiyoteru Kobayashi
    • Kiyoteru Kobayashi
    • H01L29788
    • H01L27/11521H01L27/115H01L29/42324
    • A semiconductor device and its manufacturing method which not only can solve the problem that a memory cell size determines a write/erase speed of memory cell transistors but also can increase the write/erase speed while preventing the reduction in the reliability of an insulating film between a control gate and a second-layer floating gate. Since the insulating film under a second-layer floating gate has irregularity, the second-layer floating gate itself has irregularity, whereby its surface area and hence the write/erase speed is increased. Further, since the insulating film under the second-layer floating gate has irregularity, protrusions on the surface of the second-layer floating gate are rounded. Therefore, the degree of electric field concentration is reduced, whereby the reliability of the insulating film between the control gate and the second-layer floating gate is prevented from being lowered.
    • 一种半导体器件及其制造方法,其不仅能够解决存储单元尺寸决定存储单元晶体管的写入/擦除速度的问题,而且可以提高写入/擦除速度,同时防止绝缘膜的可靠性降低 控制栅极和第二层浮栅。 由于第二层浮栅之下的绝缘膜具有不规则性,所以第二层浮栅本身具有不规则性,由此其表面积以及因此写/擦除速度增加。 此外,由于第二层浮栅之下的绝缘膜具有不规则性,所以第二层浮栅的表面上的突起是圆形的。 因此,电场浓度降低,防止控制栅极与第二层浮栅之间的绝缘膜的可靠性降低。
    • 27. 发明授权
    • Dynamic random access memory device and method of manufacturing
    • 动态随机存取存储器件及其制造方法
    • US5218217A
    • 1993-06-08
    • US568567
    • 1990-08-16
    • Hidekazu OdaKiyoteru KobayashiTakehisa Yamaguchi
    • Hidekazu OdaKiyoteru KobayashiTakehisa Yamaguchi
    • H01L27/10H01L21/8242H01L27/108H01L29/786
    • H01L27/10802H01L27/10805H01L29/78654
    • Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film. Reduced surface area occupied by each memory cell comprising a field effect transistor and a capacitor enables miniaturization of the memory cell. Electric charges generated by the impact ionization phenomenon are stored in the capacitor, so that a power consumed in a writing operation of data can be reduced.
    • 动态随机存取存储器的每个存储单元包括第一导电类型的半导体层,第二导电类型的一个和另一个杂质区,第一导电类型的栅电极,电容器杂质区和电容器电极。 第一导电类型的半导体层包括第一表面和与第一表面相对的第二表面。 在半导体层中形成彼此间隔开的一个和其它杂质区,以便限定沟道区,其中沟道表面是半导体层的第一表面的一部分。 栅电极通过栅极绝缘膜形成在沟道表面上。 在半导体层的第二表面附近形成与沟道区相对的电容器杂质区,其浓度高于半导体层的浓度。 电容器电极通过电介质膜形成在电容器杂质区上。 由包括场效应晶体管和电容器的每个存储单元占用的减小的表面积使得能够使存储单元小型化。 由电击现象产生的电荷存储在电容器中,从而可以减少数据写入操作中消耗的功率。