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21. 发明授权

US08139410B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US08139410B2
公开(公告)日：2012-03-20
申请号：US12802910
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

22. 发明授权

US08023326B2 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US08023326B2
公开(公告)日：2011-09-20
申请号：US12802894
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

23. 发明授权

US07742336B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US07742336B2
公开(公告)日：2010-06-22
申请号：US11982172
申请日：2007-11-01
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

24. 发明申请

US20090200603A1 High density vertical structure nitride flash memory 有权
标题翻译：高密度垂直结构氮化物闪存
公开(公告)号：US20090200603A1
公开(公告)日：2009-08-13
申请号：US12378108
申请日：2009-02-11
申请人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , G11C16/10 , H01L21/28282 , H01L27/108 , H01L27/10879 , H01L27/11563 , H01L27/11565 , H01L27/11568 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
摘要翻译：描述具有具有垂直和可能水平分量的存储器通道的存储器的电荷陷阱型。本发明包括用于高速和高可靠性非易失性存储器以及高密度非易失性存储器的同时空穴和电子注入操作的新操作方法。还描述了用于高密度存储器阵列和高速存储器阵列的阵列实现及其制造方法。

25. 发明授权

US06856545B2 Fast program to program verify method 有权
标题翻译：快速程序编程验证方法
公开(公告)号：US06856545B2
公开(公告)日：2005-02-15
申请号：US10371520
申请日：2003-02-20
申请人： Seiki Ogura , Tomoko Ogura , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/34 , G11C7/01
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
摘要翻译：在本发明中，描述了用于程序和程序验证的新方法。存储单元的阈值电压向上移动，然后以最小的位线和控制栅线的充电和放电进行测量。位线控制栅极线电容也用于减少所需的电压基准数量。通过使用耦合到源扩散的负载装置来减少编程电流。结果是增加了程序带宽，降低了高电压电荷泵的电流消耗。

26. 发明授权

US06628546B2 Fast program to program verify method 失效
公开(公告)号：US06628546B2
公开(公告)日：2003-09-30
申请号：US10371836
申请日：2003-02-20
申请人： Seiki Ogura , Tomoko Ogura , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

27. 发明申请

US20130094299A1 Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory 审中-公开
标题翻译：高可靠性陷阱型非易失性存储器的互补参考方法
公开(公告)号：US20130094299A1
公开(公告)日：2013-04-18
申请号：US13692503
申请日：2012-12-03
申请人： Nori Ogura , Tomoko Ogura , Seiki Ogura
发明人： Nori Ogura , Tomoko Ogura , Seiki Ogura
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/06 , G11C7/04 , G11C7/06 , G11C7/10 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0466 , G11C16/10 , G11C2211/5647
摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
摘要翻译：描述了存储器单元的互补配对的方法。这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

28. 发明授权

US08325542B2 Complementary reference method for high reliability trap-type non-volatile memory 有权
标题翻译：高可靠性陷阱型非易失性存储器的补充参考方法
公开(公告)号：US08325542B2
公开(公告)日：2012-12-04
申请号：US12583743
申请日：2009-08-25
申请人： Nori Ogura , Tomoko Ogura , Seiki Ogura
发明人： Nori Ogura , Tomoko Ogura , Seiki Ogura
IPC分类号： G11C7/00
CPC分类号： G11C16/06 , G11C7/04 , G11C7/06 , G11C7/10 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0466 , G11C16/10 , G11C2211/5647
摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
摘要翻译：描述了存储器单元的互补配对的方法。这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

29. 发明授权

US08089809B2 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US08089809B2
公开(公告)日：2012-01-03
申请号：US12802888
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

30. 发明授权

US07046553B2 Fast program to program verify method 有权
公开(公告)号：US07046553B2
公开(公告)日：2006-05-16
申请号：US10371518
申请日：2003-02-20
申请人： Seiki Ogura , Tomoko Ogura , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura , Nori Ogura
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0475 , G11C16/12 , G11C16/3454
摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

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