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21. 发明申请

US20060117155A1 Micro-threaded memory 有权
公开(公告)号：US20060117155A1
公开(公告)日：2006-06-01
申请号：US10998402
申请日：2004-11-29
申请人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
发明人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
IPC分类号： G06F12/14
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

22. 发明申请

US20060072366A1 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US20060072366A1
公开(公告)日：2006-04-06
申请号：US10955193
申请日：2004-09-30
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

23. 发明申请

US20060067146A1 Integrated circuit memory system having dynamic memory bank count and page size 有权
标题翻译：具有动态存储体积和页面大小的集成电路存储器系统
公开(公告)号：US20060067146A1
公开(公告)日：2006-03-30
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器。在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

24. 发明申请

US20050275440A1 Technique for operating a delay circuit 有权
标题翻译：用于操作延迟电路的技术
公开(公告)号：US20050275440A1
公开(公告)日：2005-12-15
申请号：US10865780
申请日：2004-06-14
申请人： Wayne Fang , Wayne Richardson , Anthony Wong
发明人： Wayne Fang , Wayne Richardson , Anthony Wong
IPC分类号： H03H11/26 , H03K19/003
CPC分类号： H03K19/00346
摘要： A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmissions of the signal through the plurality of data paths. The delay circuit may additionally generate a plurality of signals based on the staggered transmissions. Each of the plurality of data paths in the delay circuit may comprise at least one of an inverter, a logic gate, a flip-flop, a latch, a register, or a resistor-capacitor (RC) delay element.
摘要翻译：公开了一种用于操作延迟电路的技术。在一个特定的示例性实施例中，该技术可以由包括多个数据路径的延迟电路来实现。延迟电路可以接收信号。延迟电路还可能错开通过多个数据路径的信号的传输。延迟电路可以基于交错的传输额外地生成多个信号。延迟电路中的多个数据路径中的每一个可以包括逆变器，逻辑门，触发器，锁存器，寄存器或电阻 - 电容（RC）延迟元件中的至少一个。

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