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21. 发明授权

US07089362B2 Cache memory eviction policy for combining write transactions 有权
公开(公告)号：US07089362B2
公开(公告)日：2006-08-08
申请号：US10035034
申请日：2001-12-27
申请人： Kenneth C. Creta , Robert Blankenship , Robert George
发明人： Kenneth C. Creta , Robert Blankenship , Robert George
IPC分类号： G06F12/00
CPC分类号： G06F12/0804
摘要： Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

22. 发明授权

US06694383B2 Handling service requests 有权
公开(公告)号：US06694383B2
公开(公告)日：2004-02-17
申请号：US10008595
申请日：2001-12-06
申请人： Thai Q. Nguyen , Robert J. Miller , Kenneth C. Creta
发明人： Thai Q. Nguyen , Robert J. Miller , Kenneth C. Creta
IPC分类号： G06F300
CPC分类号： G06F13/4031 , G06F2213/0024
摘要： A first component that stores information about requests for information directed to an interface (e.g., a bus of a computer system connected to components), receives an indication of a request sent by a second component to the interface. The first component sends an identifier for a subsequent request to the second component.

23. 发明授权

US08046539B2 Method and apparatus for the synchronization of distributed caches 有权
标题翻译：分布式缓存同步的方法和装置
公开(公告)号：US08046539B2
公开(公告)日：2011-10-25
申请号：US12479541
申请日：2009-06-05
申请人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
发明人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译：一种用于同步分布式缓存的方法和装置。更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。

24. 发明申请

US20090240894A1 METHOD AND APARATUS FOR THE SYNCHRONIZATION OF DISTRIBUTED CACHES 有权
标题翻译：分布式快照同步的方法与方法
公开(公告)号：US20090240894A1
公开(公告)日：2009-09-24
申请号：US12479541
申请日：2009-06-05
申请人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
发明人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译：一种用于同步分布式缓存的方法和装置。更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。

25. 发明申请

US20090031058A1 Methods and Apparatuses for Flushing Write-Combined Data From A Buffer 有权
标题翻译：用于从缓冲器冲洗写入组合数据的方法和装置
公开(公告)号：US20090031058A1
公开(公告)日：2009-01-29
申请号：US11966760
申请日：2007-12-28
申请人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
发明人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/1631 , G06F12/0831 , G06F12/0879 , G06F12/0897 , H04L69/12
摘要： Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.
摘要翻译：将写入组合数据从存储器中的缓冲器冲洗到输入/输出（I / O）设备的方法和装置。

26. 发明授权

US07353301B2 Methodology and apparatus for implementing write combining 有权
标题翻译：实现写入组合的方法和设备
公开(公告)号：US07353301B2
公开(公告)日：2008-04-01
申请号：US10977235
申请日：2004-10-29
申请人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
发明人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
IPC分类号： G06F3/00 , G06G3/00
CPC分类号： G06F13/1631 , G06F12/0831 , G06F12/0879 , G06F12/0897 , H04L69/12
摘要： Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.
摘要翻译：本文介绍了使用推送模型的计算机系统中的写入组合。在一个实施例中，该方法包括：响应于冲洗缓冲器的刷新请求，创建一个或多个具有描述符的数据包，以及存储在缓冲区中的检测到的写入事务的数据，该数据被分配给可写入可组合范围，并发送（推送）这些数据包到网络I / O设备。

27. 发明授权

US07206865B2 Apparatus and method for combining writes to I/O 有权
标题翻译：用于将写入组合到I / O的装置和方法
公开(公告)号：US07206865B2
公开(公告)日：2007-04-17
申请号：US10402125
申请日：2003-03-28
申请人： Kenneth C. Creta , Gregory D. Cummings , Sujoy Sen
发明人： Kenneth C. Creta , Gregory D. Cummings , Sujoy Sen
IPC分类号： G06F13/14
CPC分类号： G06F13/4027
摘要： An apparatus and method for outbound I/O write-combining are described. In one embodiment the method includes the detection of a write transaction request directed to an I/O device. Once detected, it is determined whether an address associated with the detected write transaction falls within a predetermined write-combinable range of the memory mapped I/O space assigned to the I/O device. When the transaction address falls within a write-combinable range, data associated with the detected write transaction is stored within a buffer corresponding to the transaction address. Accordingly, one embodiment of the present invention provides write-combining for data written to an I/O port associated with a memory mapped I/O address space.
摘要翻译：描述了用于出站I / O写入组合的装置和方法。在一个实施例中，该方法包括检测针对I / O设备的写事务请求。一旦检测到，确定与检测到的写事务相关联的地址是否落入分配给I / O设备的存储器映射I / O空间的预定的可写入可组合范围内。当交易地址落在可写入组合范围内时，与检测到的写事务相关联的数据被存储在对应于交易地址的缓冲器内。因此，本发明的一个实施例提供了写入到与存储器映射的I / O地址空间相关联的I / O端口的数据的写入组合。

28. 发明授权

US06216247B1 32-bit mode for a 64-bit ECC capable memory subsystem 失效
标题翻译： 32位模式，用于支持64位ECC的内存子系统
公开(公告)号：US06216247B1
公开(公告)日：2001-04-10
申请号：US09087390
申请日：1998-05-29
申请人： Kenneth C. Creta , Elliot Garbus
发明人： Kenneth C. Creta , Elliot Garbus
IPC分类号： G11C2900
CPC分类号： G06F11/10
摘要： A 32-bit mode operation for a typical 64-bit ECC memory subsystem. In 32-bit mode, each data block will have an 8-bit ECC value, which is consistent with ECC values generated for 64-bit data. This is achieved by prefixing the data with 32 zeroes. When reading out data, memory faults can be corrected and detected using ECC techniques on a zero prefixed data block that is read out of the memory. This allows a memory subsystem to be optimized for bandwidth and latency depending upon this application.
摘要翻译：用于典型64位ECC内存子系统的32位模式操作。在32位模式下，每个数据块将具有8位ECC值，这与为64位数据生成的ECC值一致。这是通过将数据前缀为32个零来实现的。当读出数据时，可以使用ECC技术对内存中读出的零前缀数据块进行修正和检测。这允许根据该应用程序优化内存子系统的带宽和延迟。

29. 发明授权

US6088762A Power failure mode for a memory controller 失效
标题翻译：内存控制器的电源故障模式
公开(公告)号：US6088762A
公开(公告)日：2000-07-11
申请号：US100229
申请日：1998-06-19
申请人： Kenneth C. Creta
发明人： Kenneth C. Creta
IPC分类号： G06F12/08 , G11C11/403 , G11C11/404 , G11C11/406 , G11C11/407 , G06F12/16
CPC分类号： G11C11/406 , G11C11/404
摘要： A power failure mode for a memory controller, such as a memory controller used in an input/output processor, which, when the memory controller has system power, refreshes a memory unit, such as an SDRAM memory unit, as required to maintain the memory image. In one embodiment, when a power failure occurs, the memory controller issues a self-refresh command to the memory, which has battery-backup power. A PCI reset signal may be used to determine when a power failure has occurred. The self-refresh command places the memory in a self-refresh mode, and a programmable logic device may be used to ensure that a clock enable signal input to the memory maintains the self-refresh mode. When system power returns, the memory controller resumes refreshing the memory.
摘要翻译：用于存储器控制器的电源故障模式，诸如在输入/输出处理器中使用的存储器控制器，当存储器控制器具有系统电源时，根据需要刷新诸如SDRAM存储器单元的存储器单元以维持存储器图片。在一个实施例中，当发生电源故障时，存储器控制器向具有电池备用电力的存储器发出自刷新命令。可以使用PCI复位信号来确定何时发生电源故障。自刷新命令将存储器置于自刷新模式，并且可编程逻辑器件可用于确保输入到存储器的时钟使能信号保持自刷新模式。当系统电源恢复时，存储器控制器恢复刷新存储器。

30. 发明申请

US20150058524A1 BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION 审中-公开
标题翻译：相关链接和内存扩展之间的双向功能
公开(公告)号：US20150058524A1
公开(公告)日：2015-02-26
申请号：US13808314
申请日：2012-01-04
申请人： Kenneth C. Creta , Jason W. Horihan , Robert G. Blankenship , Kai Cheng
发明人： Kenneth C. Creta , Jason W. Horihan , Robert G. Blankenship , Kai Cheng
IPC分类号： G06F3/06 , G11C13/00 , G11C14/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/16 , G06F13/4234 , G06F2206/1014 , G11C13/0002 , G11C14/009
摘要： Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.
摘要翻译：描述了在相干链路和存储器扩展之间提供双模功能相关的方法和装置。在一个实施例中，处理器经由相干互连耦合到一个或多个代理。处理器还通过链路逻辑耦合到一个或多个双列直插式内存模块（DIMM）。该逻辑支持基于单个数据位读取或写入指向一个或多个DIMM的命令。还公开并要求保护其他实施例。

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