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21. 发明授权

US08310135B2 Piezoelectric thin film element and piezoelectric thin film device including the same 有权
标题翻译：压电薄膜元件和包括该压电薄膜元件的压电薄膜器件
公开(公告)号：US08310135B2
公开(公告)日：2012-11-13
申请号：US12797340
申请日：2010-06-09
申请人： Kazufumi Suenaga , Kenji Shibata , Hideki Sato , Akira Nomoto
发明人： Kazufumi Suenaga , Kenji Shibata , Hideki Sato , Akira Nomoto
IPC分类号： H01L41/187
CPC分类号： H01L41/18
摘要： A piezoelectric thin film element is provided, including on a substrate: a piezoelectric thin film expressed by a general formula (NaxKyLiz)NbO3 (0≦x≦1, 0≦y≦1, 0≦z≦0.2, x+y+z=1); and an upper electrode laminated thereon, wherein the piezoelectric thin film has a crystal structure of any one of a pseudo-cubic crystal, a tetragonal crystal, or an orthorhombic crystal, or has a crystal structure of coexistence of at least two of the pseudo-cubic crystal, the tetragonal crystal, or the orthorhombic crystal, and in such crystal structures, there is a coexistence of (001) oriented crystal grains oriented in (001) direction, and (111) oriented crystal grains oriented in (111) direction, with an angle formed by at least one of the crystal axes of the crystal grains and a normal line of the substrate surface set to be in a range of 0° to 10°.
摘要翻译：提供了一种压电薄膜元件，其包括在基板上：由通式（NaxKyLiz）NbO3（0＆amp; nlE; x＆lt; lE; 1,0＆amp; nlE; y＆nlE; 1,0＆amp; nlE; z＆nlE; 0.2，x + y + z表示的压电薄膜 = 1）; 其上层叠有上电极，其中，所述压电薄膜具有假立方晶体，四方晶体或正交晶体中的任一种的晶体结构，或者具有至少两个所述伪晶体的晶体结构，立方晶体，四方晶体或正交晶体，并且在这样的晶体结构中，（001）取向的（001）取向晶粒与（111）方向取向的（111）取向晶粒共存，由晶粒的晶轴和衬底表面的法线中的至少一个形成的角度设定在0°至10°的范围内。

22. 发明授权

US08304966B2 Piezoelectric thin film element and manufacturing method of the piezoelectric thin film element, piezoelectric thin film device 有权
标题翻译：压电薄膜元件和压电薄膜元件的制造方法，压电薄膜器件
公开(公告)号：US08304966B2
公开(公告)日：2012-11-06
申请号：US12819424
申请日：2010-06-21
申请人： Kazufumi Suenaga , Kenji Shibata , Hideki Sato , Akira Nomoto
发明人： Kazufumi Suenaga , Kenji Shibata , Hideki Sato , Akira Nomoto
IPC分类号： H01L41/187
CPC分类号： C04B35/495 , C04B2235/3201 , C04B2235/3203 , C04B2235/3251 , H01L41/187 , H01L41/1873 , H01L41/316
摘要： To provide a piezoelectric thin film element capable of improving piezoelectric characteristics and realize a piezoelectric thin film device with high performance and high reliability, comprising: a substrate; and a piezoelectric thin film formed on the substrate by a sputtering method, with perovskite oxide expressed by (NaxKyLiz)NbO3 (0≦x≦1, 0≦y≦1, 0≦z≦0, 2, x+y+z=1) as a main phase, wherein an absolute value of an internal stress of the piezoelectric thin film is 1.6 GPa or less.
摘要翻译：为了提供能够改善压电特性并实现具有高性能和高可靠性的压电薄膜器件的压电薄膜元件，包括：衬底; （NaxKyLiz）NbO3（0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1,0＆amp; nlE; z＆nlE; 0,2，x + y + z = 0）表示的由钙钛矿氧化物形成的基板上的压电薄膜， 1）作为主相，其中压电薄膜的内应力的绝对值为1.6GPa以下。

23. 发明申请

US20120025668A1 Piezoelectric thin film element 审中-公开
标题翻译：压电薄膜元件
公开(公告)号：US20120025668A1
公开(公告)日：2012-02-02
申请号：US13137580
申请日：2011-08-26
申请人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
发明人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
IPC分类号： H01L41/047 , H01L41/113 , H01L41/09
CPC分类号： H01L41/047 , H01L41/0805 , H01L41/1873 , H01L41/316
摘要： A piezoelectric thin film element includes a bottom electrode, a piezoelectric layer, and a top electrode on a substrate. The piezoelectric layer includes, as a main phase, a perovskite-type oxide. The bottom electrode has a surface roughness of not more than 0.86 nm in arithmetic mean roughness Ra or not more than 1.1 nm in root mean square roughness Rms. The bottom electrode has a (111) preferential orientation in a direction perpendicular to the substrate.
摘要翻译：压电薄膜元件包括底电极，压电层和衬底上的顶电极。作为主相，压电体层包含钙钛矿型氧化物。底部电极在算术平均粗糙度Ra中的表面粗糙度不大于0.86nm，均方根粗糙度Rms下的表面粗糙度不大于1.1nm。底部电极在垂直于衬底的方向上具有（111）优先取向。

24. 发明授权

US08058779B2 Piezoelectric thin film element 有权
标题翻译：压电薄膜元件
公开(公告)号：US08058779B2
公开(公告)日：2011-11-15
申请号：US12588484
申请日：2009-10-16
申请人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
发明人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
IPC分类号： H01L41/187
CPC分类号： H01L41/047 , H01L41/0805 , H01L41/1873 , H01L41/316
摘要： A piezoelectric thin film element includes a bottom electrode, a piezoelectric layer and a top electrode on a substrate. The piezoelectric layer includes as a main phase a perovskite-type oxide represented by (NaxKyLiz)NbO3 (0≦x≦1, 0≦y≦1, 0≦z≦0.2, x+y+z=1), and the bottom electrode includes a surface roughness of not more than 0.86 nm in arithmetic mean roughness Ra or not more than 1.1 nm in root mean square roughness Rms.
摘要翻译：压电薄膜元件包括底电极，压电层和衬底上的顶电极。压电层包括由（NaxKyLiz）NbO 3（0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1,0＆amp; nlE; z＆nlE; 0.2，x + y + z = 1）表示的钙钛矿型氧化物，电极包括算术平均粗糙度Ra不大于0.86nm的表面粗糙度或均方根粗糙度Rms不大于1.1nm的表面粗糙度。

25. 发明申请

US20100141099A1 Piezoelectric thin film element 有权
标题翻译：压电薄膜元件
公开(公告)号：US20100141099A1
公开(公告)日：2010-06-10
申请号：US12588484
申请日：2009-10-16
申请人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
发明人： Kazufumi Suenaga , Kenji Shibata , Fumihito Oka , Hideki Sato
IPC分类号： H01L41/047
CPC分类号： H01L41/047 , H01L41/0805 , H01L41/1873 , H01L41/316
摘要： A piezoelectric thin film element includes a bottom electrode, a piezoelectric layer and a top electrode on a substrate. The piezoelectric layer includes as a main phase a perovskite-type oxide represented by (NaxKyLiz)NbO3 (0
摘要翻译：压电薄膜元件包括底电极，压电层和衬底上的顶电极。压电层包括由（NaxKyLiz）NbO 3（0

26. 发明授权

US08084925B2 Piezoelectric thin film elemental device, sensor and actuator 有权
标题翻译：压电薄膜元件，传感器和执行器
公开(公告)号：US08084925B2
公开(公告)日：2011-12-27
申请号：US12427348
申请日：2009-04-21
申请人： Kenji Shibata , Fumihito Oka , Kazufumi Suenaga
发明人： Kenji Shibata , Fumihito Oka , Kazufumi Suenaga
IPC分类号： H01L41/08
CPC分类号： H01L41/1873 , H01L41/0815 , H01L41/094 , H01L41/316
摘要： A piezoelectric thin film element has a piezoelectric thin film on a substrate, the piezoelectric thin film has a (K1-x,Nax)NbO3thin film expressed by a compositional formula (K1-xNax)NbO3(0
摘要翻译：压电薄膜元件在基板上具有压电薄膜，压电薄膜具有由组成式（K1-xNax）NbO3（0

27. 发明授权

US06867446B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06867446B2
公开(公告)日：2005-03-15
申请号：US10268709
申请日：2002-10-11
申请人： Miharu Otani , Jun Tanaka , Kazufumi Suenaga , Kiyoshi Ogata
发明人： Miharu Otani , Jun Tanaka , Kazufumi Suenaga , Kiyoshi Ogata
IPC分类号： H01L21/768 , H01L21/02 , H01L21/312 , H01L21/316 , H01L21/8246 , H01L23/522 , H01L27/105 , H01L31/062
CPC分类号： H01L28/57 , H01L21/02118 , H01L21/02164 , H01L21/02175 , H01L21/02197 , H01L21/022 , H01L21/312 , H01L21/31604 , H01L21/31612 , H01L28/55 , H01L2224/45144 , H01L2224/48247 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： In a semiconductor memory device having a capacitor layer comprising a dielectric film or a ferroelectric film, as an interlayer insulation film formed between the capacitor and a wiring layer formed at the upper part thereof or an insulation film which covers the wiring layer, a multilayered film is used which consists of a first insulation film and a second insulation film laid upon the other; the former being a lower layer and being formed of an organic film, and the latter being an upper layer and being formed of a hard-mask material. This makes it possible to prevent thin film comprised of a dielectric material or a ferroelectric material from any deterioration caused by the hydrogen and water contained in the interlayer insulation film and passivation film of the semiconductor memory device and also by the stress of these films.
摘要翻译：在具有电介质膜或铁电体膜的电容器层的半导体存储器件中，作为形成在电容器和形成于其上部的布线层之间的层间绝缘膜或覆盖布线层的绝缘膜，具有多层膜被使用，其由第一绝缘膜和彼此叠置的第二绝缘膜组成; 前者为下层，由有机膜形成，后者为上层，由硬掩模材料形成。这使得可以防止由介电材料或铁电材料构成的薄膜由于半导体存储器件的层间绝缘膜和钝化膜中所含的氢和水引起的任何劣化，以及这些膜的应力。

28. 发明授权

US06897503B2 Semiconductor memory device and manufacturing process for the same 有权
标题翻译：半导体存储器件及其制造工艺相同
公开(公告)号：US06897503B2
公开(公告)日：2005-05-24
申请号：US10861500
申请日：2004-06-07
申请人： Miharu Otani , Jun Tanaka , Kazufumi Suenaga , Kiyoshi Ogata
发明人： Miharu Otani , Jun Tanaka , Kazufumi Suenaga , Kiyoshi Ogata
IPC分类号： H01L21/768 , H01L21/02 , H01L21/312 , H01L21/316 , H01L21/8246 , H01L23/522 , H01L27/105 , H01L31/062
CPC分类号： H01L28/57 , H01L21/02118 , H01L21/02164 , H01L21/02175 , H01L21/02197 , H01L21/022 , H01L21/312 , H01L21/31604 , H01L21/31612 , H01L28/55 , H01L2224/45144 , H01L2224/48247 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： In a semiconductor memory device having a capacitor layer comprising a dielectric film or a ferroelectric film, as an interlayer insulation film formed between the capacitor and a wiring layer formed at the upper part thereof or an insulation film which covers the wiring layer, a multilayered film is used which consists of a first insulation film and a second insulation film laid upon the other; the former being a lower layer and being formed of an organic film, and the latter being an upper layer and being formed of a hard-mask material.This makes it possible to prevent thin films comprised of a dielectric material or a ferroelectric material from any deterioration caused by the hydrogen and water contained in the interlayer insulation film and passivation film of the semiconductor memory device and also by the stress of these films.
摘要翻译：在具有电介质膜或铁电体膜的电容器层的半导体存储器件中，作为形成在电容器和形成于其上部的布线层之间的层间绝缘膜或覆盖布线层的绝缘膜，具有多层膜被使用，其由第一绝缘膜和彼此叠置的第二绝缘膜组成; 前者为下层，由有机膜形成，后者为上层，由硬掩模材料形成。这使得可以防止由介电材料或铁电材料构成的薄膜由于半导体存储器件的层间绝缘膜和钝化膜中所含的氢和水引起的任何劣化，以及这些膜的应力。

29. 发明授权

US06623986B2 Method of manufacturing a ferroelectric memory device 失效
标题翻译：铁电存储器件的制造方法
公开(公告)号：US06623986B2
公开(公告)日：2003-09-23
申请号：US09984465
申请日：2001-10-30
申请人： Kiyoshi Ogata , Kazuhiko Horikoshi , Kazufumi Suenaga , Hisayuki Kato , Keiichi Yoshizumi , Masahito Yamazaki
发明人： Kiyoshi Ogata , Kazuhiko Horikoshi , Kazufumi Suenaga , Hisayuki Kato , Keiichi Yoshizumi , Masahito Yamazaki
IPC分类号： H01L2100
CPC分类号： H01L28/57 , H01L27/1203
摘要： Along life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrode 8 and a degradation preventive layer at the boundary of ferroelectric layer 7/electrodes 6, 8, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer 7/upper electrode 8. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.
摘要翻译：通过在铁氧体层7 /电极6的边界上的上保护电极和上电极8以及降解防止层上设置多个防结层，可以获得使用薄铁电体膜电容器作为记忆电容器的寿命铁电存储器件或者提供在铁电层7 /上电极8的边界处减少改性层的步骤。这提供了一种薄铁电薄膜电容器，其经受较少的疲劳和压印，并且具有较低的铁电特性降低以达到长寿命铁电存储器件。

30. 发明授权

US06995058B2 Semiconductor memory device and manufacturing method thereof 失效
公开(公告)号：US06995058B2
公开(公告)日：2006-02-07
申请号：US10183669
申请日：2002-06-28
申请人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
发明人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
IPC分类号： H01L21/8242
CPC分类号： H01L28/55 , G11C11/22 , H01L21/31691
摘要： The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

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