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21. 发明授权

US5677219A Process for fabricating a DRAM trench capacitor 失效
标题翻译：制造DRAM沟槽电容器的工艺
公开(公告)号：US5677219A
公开(公告)日：1997-10-14
申请号：US365649
申请日：1994-12-29
申请人： Carlos A. Mazure , Christian G. Dieseldorff
发明人： Carlos A. Mazure , Christian G. Dieseldorff
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861
摘要： An improved trench cell capacitor for a memory cell and process for fabricating the same. The process includes the steps of forming a trench within a semiconductor body; forming a dielectric layer peripherally within the trench and filling at least a portion of the trench by epitaxially growing semiconductor material therein. The epitaxially grown semiconductor material is void and seam-free, resulting in a robust trench cell that is highly reliable, thereby improving process yield.
摘要翻译：一种用于存储单元的改进的沟槽单元电容器及其制造方法。该方法包括在半导体本体内形成沟槽的步骤; 在沟槽内周边形成电介质层，并通过在其中外延生长半导体材料来填充沟槽的至少一部分。外延生长的半导体材料是空隙和无缝的，导致稳定的沟槽电池，其高度可靠，从而提高了工艺产量。

22. 发明授权

US5061647A ITLDD transistor having variable work function and method for fabricating the same 失效
标题翻译：具有可变功函数的ITLDD晶体管及其制造方法
公开(公告)号：US5061647A
公开(公告)日：1991-10-29
申请号：US597946
申请日：1990-10-12
申请人： Scott S. Roth , Carlos A. Mazure , Kent J. Cooper , Wayne J. Ray , Michael P. Woo , Jung-Hui Lin
发明人： Scott S. Roth , Carlos A. Mazure , Kent J. Cooper , Wayne J. Ray , Michael P. Woo , Jung-Hui Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/4983 , H01L29/7836
摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.
摘要翻译：一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

23. 发明授权

US5314834A Field effect transistor having a gate dielectric with variable thickness 失效
标题翻译：场效应晶体管具有可变厚度的栅极电介质
公开(公告)号：US5314834A
公开(公告)日：1994-05-24
申请号：US750155
申请日：1991-08-26
申请人： Carlos A. Mazure , Marius K. Orlowski
发明人： Carlos A. Mazure , Marius K. Orlowski
IPC分类号： H01L21/336 , H01L29/423 , H01L21/265 , H01L29/68
CPC分类号： H01L29/66575 , H01L29/42368 , H01L29/6659 , H01L29/66628 , Y10S438/981
摘要： A field effect transistor, FET, (11) having a gate dielectric of varying thickness (14, 24) to improve device performance. The FET (11) is made on a substrate (10) and has a control electrode, or gate (16), and two current electrodes, or source and drain regions (28), which are separated by a channel region. The gate (16) is separated from the channel region by a gate dielectric. The gate dielectric has a centrally located first region that is of a first thickness (14) and a second region which is adjacent a perimeter of the first region that is of a second thickness (24). The second thickness (24) is made greater than the first thickness (14).
摘要翻译：具有不同厚度（14,24）的栅极电介质的场效应晶体管FET（11），以提高器件性能。 FET（11）在基板（10）上形成，并具有控制电极或栅极（16）以及由通道区域分开的两个电流电极或源极和漏极区域（28）。栅极（16）通过栅极电介质与沟道区分离。栅极电介质具有居中定位的第一区域，其具有第一厚度（14）和与第二区域的第二厚度（24）的周边相邻的第二区域。第二厚度（24）被制成大于第一厚度（14）。

24. 发明授权

US5538922A Method for forming contact to a semiconductor device 失效
标题翻译：形成与半导体器件的接触的方法
公开(公告)号：US5538922A
公开(公告)日：1996-07-23
申请号：US378990
申请日：1995-01-25
申请人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
发明人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
IPC分类号： H01L21/60 , H01L21/46
CPC分类号： H01L21/76897 , Y10S148/02 , Y10S438/97
摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.
摘要翻译：接触形成在半导体器件（10）中，与底层的形貌或间距无关。在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。在绝缘层上沉积蚀刻停止层（20）。在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

25. 发明授权

US06207494B1 Isolation collar nitride liner for DRAM process improvement 有权
标题翻译：用于DRAM工艺改进的隔离环氮化物衬垫
公开(公告)号：US06207494B1
公开(公告)日：2001-03-27
申请号：US09282122
申请日：1999-03-31
申请人： Christoff Graimann , Angelika Schulz , Carlos A. Mazure , Christian Dieseldorff
发明人： Christoff Graimann , Angelika Schulz , Carlos A. Mazure , Christian Dieseldorff
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, a collar is formed in an upper portion of the trench by forming an oxide layer in the upper portion. A nitride layer on the oxide layer. The trench is then filled with semiconductor material. For example, a semiconductor region can be epitaxially grown to fill the trench.
摘要翻译：可以使用制造沟槽单元电容器的方法来形成DRAM单元。在一个实施例中，在半导体衬底内形成沟槽。沟槽衬有介电层，例如ONO层。在衬套沟槽之后，通过在上部形成氧化物层，在沟槽的上部形成套环。氧化物层上的氮化物层。然后用半导体材料填充沟槽。例如，半导体区域可以外延生长以填充沟槽。

26. 发明授权

US5219793A Method for forming pitch independent contacts and a semiconductor device having the same 失效
标题翻译：用于形成俯仰独立触点的方法和具有该触点的半导体器件
公开(公告)号：US5219793A
公开(公告)日：1993-06-15
申请号：US709554
申请日：1991-06-03
申请人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
发明人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
IPC分类号： H01L21/60
CPC分类号： H01L21/76897 , Y10S148/02 , Y10S438/97
摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.
摘要翻译：接触形成在半导体器件（10）中，与底层的形貌或间距无关。在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。在绝缘层上沉积蚀刻停止层（20）。在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

27. 发明授权

US5210435A ITLDD transistor having a variable work function 失效
标题翻译：具有可变功函数的ITLDD晶体管
公开(公告)号：US5210435A
公开(公告)日：1993-05-11
申请号：US745652
申请日：1991-08-16
申请人： Scott S. Roth , Carlos A. Mazure , Kent J. Cooper , Wayne J. Ray , Michael P. Woo , Jung-Hui Lin
发明人： Scott S. Roth , Carlos A. Mazure , Kent J. Cooper , Wayne J. Ray , Michael P. Woo , Jung-Hui Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/4983 , H01L29/7836
摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.
摘要翻译：一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

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