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21. 发明授权

US5462629A Surface processing apparatus using neutral beam 失效
标题翻译：使用中性梁的表面处理装置
公开(公告)号：US5462629A
公开(公告)日：1995-10-31
申请号：US111598
申请日：1993-08-25
申请人： Naoki Kubota , Osamu Kinoshita , Yoshio Kaneko
发明人： Naoki Kubota , Osamu Kinoshita , Yoshio Kaneko
IPC分类号： H01J37/305 , C23F1/02
CPC分类号： H01J37/3053 , H01J2237/0041 , H01J2237/3151
摘要： A surface processing apparatus and a dry etching method using a neutral beam. The surface processing apparatus comprises a plasma chamber for generating a plasma P, a neutralizing chamber for converting an ion beam extracted from the plasma P by an ion extracting electrode into the neutral beam, and a processing chamber for introducing therein the neutral beam and etching a substrate S to be processed using the neutral beam. There is also provided a static electric field lens comprising two spaced first electrodes provided on the inner periphery of the neutralizing chamber and a second electrode interposed therebetween so as to obtain the neutral beams having low energy and high flux.
摘要翻译：表面处理装置和使用中性光束的干蚀刻方法。表面处理装置包括用于产生等离子体P的等离子体室，用于将从等离子体P提取的离子束由离子提取电极转换成中性光束的中和室，以及用于在其中引入中性光束并蚀刻要使用中性光束处理的基板S。还提供了一种静电电场透镜，包括设置在中和室的内周上的两个间隔开的第一电极和插在其间的第二电极，以获得具有低能量和高通量的中性光束。

22. 发明授权

US5140618A Frame synchronization circuit 失效
标题翻译：帧同步电路
公开(公告)号：US5140618A
公开(公告)日：1992-08-18
申请号：US651013
申请日：1991-02-05
申请人： Osamu Kinoshita , Takako Mori , Hideki Ishibashi , Hiroyuki Ibe , Takehiko Atsumi
发明人： Osamu Kinoshita , Takako Mori , Hideki Ishibashi , Hiroyuki Ibe , Takehiko Atsumi
IPC分类号： H04J3/00 , H04J3/06 , H04L7/08
CPC分类号： H04J3/0608
摘要： In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors of a first synchronization detecting circuit detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit holds outputs of the pattern detectors, and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit is delayed by a time required for the above-mentioned processing, and supplied to a selector, which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal.
摘要翻译：在帧同步电路中，包括由一帧中的M个位组成的帧同步码的串行数据信号由串/并转换电路转换为2M-1位的并行数据信号。 M个第一同步检测电路的模式检测器从并行数据信号检测帧同步码的第一块的码模式。选择信号发生电路保持图案检测器的输出，并输出它们作为指定分配给检测同步码模式的图案检测器的位位置的选择信号。串行/并行转换电路的输出被延迟上述处理所需的时间，并提供给选择器，选择器输出与由选择信号指定的位位置对应的M位数据信号。

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