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21. 发明申请

US20070285968A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285968A1
公开(公告)日：2007-12-13
申请号：US11761400
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体基板上的用于数据读写的单元阵列下面的读/写电路，其中可变电阻元件包括由包含至少两种类型的阳离子元素的复合化合物组成的记录层，至少一种阳离子元素是具有“d”轨道的过渡元素，其中电子未完全填充，相邻阳离子元素之间的最短距离为0.32nm以下。

22. 发明申请

US20070285965A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285965A1
公开(公告)日：2007-12-13
申请号：US11761333
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0007 , G11C5/02 , G11C13/0004 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/147 , Y10S438/936
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在基板上方，位线字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 以及第三垂直布线，用于将字线连接到读/写电路，其中存储单元包括可变电阻元件，用于存储作为信息的电阻值，该电阻值具有由A

23. 发明申请

US20060203541A1 Phase change memory device 审中-公开
标题翻译：相变存储器件
公开(公告)号：US20060203541A1
公开(公告)日：2006-09-14
申请号：US10548575
申请日：2003-03-18
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C11/36 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.
摘要翻译：相变存储器件包括衬底，堆叠在衬底上的多个单元阵列，每个单元阵列包括多个存储器单元的矩阵布局，每个存储器单元作为数据存储为可由相变所确定的电阻值，写入电路，被配置为以多个单元阵列中的两个相邻存储单元构成的对单元，以将该单元格中的一个写入高电阻值状态，并将另一个单元写入低电阻值状态;以及读取电路被配置为读取对单元的互补电阻值状态作为一位数据。

24. 发明申请

US20060028906A1 Clock-synchronous semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US20060028906A1
公开(公告)日：2006-02-09
申请号：US11247222
申请日：2005-10-12
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2207/2254
摘要： A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.
摘要翻译：半导体器件包括存储单元阵列，控制部分和等待时间设置电路。所述控制部被配置为接收时钟信号和控制信号，并且被配置为在所述控制信号被断言之后与所述时钟信号同步地输出多个数据。延迟设置电路被配置为设置延迟N，并且延迟设置电路包括至少一个开关，其通过使用外部提供的信号来固定等待时间。

25. 发明授权

US06928028B2 Synchronous dynamic random access memory for burst read/write operations 失效
标题翻译：用于突发读/写操作的同步动态随机存取存储器
公开(公告)号：US06928028B2
公开(公告)日：2005-08-09
申请号：US10891162
申请日：2004-07-14
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C8/12
CPC分类号： G11C7/10 , G11C7/103 , G11C7/1072 , G11C11/4096
摘要： A synchronous DRAM has cell arrays arranged in matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks, is used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes a first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.
摘要翻译：同步DRAM具有排列成矩阵的单元阵列，被划分为异步访问的存储体和用于在单元阵列之间传送数据的n位I / O总线。在DRAM中，银行分为m个块，位于相邻bank之间的n位I / O总线用于相邻bank之间的时间共享，n位I / O总线用于在相邻bank之间进行时间共享共同的组合被分组为n / m位I / O总线，每个m个块的每个块的每n / m位，并且在每个存储体的每个块中，数据输入/输出在n / 每个块中的m位I / O总线和数据总线。同步DRAM包括用于控制突发数据传输的第一和第二内部时钟系统，其中当内部时钟系统中的一个被驱动时，突发数据传输开始，其中一串突发数据正在与外部时钟信号同步传输立即由选定的内部时钟系统。

26. 发明申请

US20050047237A1 Data write circuit in memory system and data write method 失效
标题翻译：数据写入电路在内存系统和数据写入方式
公开(公告)号：US20050047237A1
公开(公告)日：2005-03-03
申请号：US10964904
申请日：2004-10-14
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C7/00
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C2207/002 , G11C2207/229
摘要： There is disclosed a memory system including a memory cell array, a sense amplifier circuit, a write circuit, a level setting circuit, a column decoder, a data line, and a sense amplifier control circuit. The level setting circuit sets external input data to substantially the same level as a read potential difference level from the memory cell. The external input data whose level has been set by the level setting circuit is transferred to the sense amplifier selected by the column decoder via the data line. The sense amplifier control circuit activates the selected sense amplifier so as to write the external input data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.
摘要翻译：公开了一种包括存储单元阵列，读出放大器电路，写入电路，电平设置电路，列解码器，数据线以及读出放大器控制电路的存储器系统。电平设置电路将外部输入数据设置为与来自存储单元的读取电位差电平基本相同的电平。电平已由电平设置电路设置的外部输入数据经由数据线传输到由列解码器选择的读出放大器。读出放大器控制电路激活所选择的读出放大器，以便以与从存储器单元的数据读取时间基本相同的顺序将外部输入数据写入存储单元。

27. 发明授权

US06647478B2 Semiconductor memory device 失效
公开(公告)号：US06647478B2
公开(公告)日：2003-11-11
申请号：US10175085
申请日：2002-06-20
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

28. 发明授权

US06625082B2 Test circuit for testing semiconductor memory 失效
公开(公告)号：US06625082B2
公开(公告)日：2003-09-23
申请号：US10315598
申请日：2002-12-10
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/10 , G11C7/18 , G11C29/12
摘要： Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.

29. 发明授权

US06430101B1 Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory 失效
标题翻译：使用反熔丝的保险丝电路和用于搜索半导体存储器中的失败地址的方法
公开(公告)号：US06430101B1
公开(公告)日：2002-08-06
申请号：US09931024
申请日：2001-08-17
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/16 , G11C29/44
摘要： A fuse circuit comprises first and second electric fuses, a differential amplifier and a switch circuit. The first and second electric fuses have their respective current characteristics changed when a voltage of a predetermined level or more is applied thereto. The differential amplifier receives two voltage signals based on the current characteristics of the first and second electric fuses, outputs a predetermined voltage on the basis of a difference in voltage between the two voltage signals, and amplifies the predetermined voltage. The memory circuit stores an output from the differential amplifier. The switch circuit connects and disconnects the differential amplifier to and from the memory circuit.
摘要翻译：熔丝电路包括第一和第二电熔丝，差动放大器和开关电路。当施加预定水平或更高的电压时，第一和第二电熔丝的各自的电流特性发生变化。差分放大器基于第一和第二电熔丝的电流特性接收两个电压信号，基于两个电压信号之间的电压差输出预定电压，并放大预定电压。存储电路存储差分放大器的输出。开关电路将差分放大器与存储电路断开并断开。

30. 发明授权

US06226209B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06226209B1
公开(公告)日：2001-05-01
申请号：US09605446
申请日：2000-06-28
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/808 , G11C29/846
摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.
摘要翻译：本发明的目的是提供一种半导体存储器件，其中即使对于较大数量的位也可有效地修复故障。在能够在接收到地址时同时交换多个数据的多位存储器中，通常用于每个I / O的备用DQ线（15c），备用读出放大器电路（13c），备用列开关（14c），用于存储其中发生故障的DQ线的地址的保险丝盒（20）和用于存储故障DQ的I / O的熔丝电路（21-1,21-2 ...）排列的行被排列以补救每个I / O的故障。由于只有属于发生故障的一个I / O的存储单元被替换，所以不执行不必要的替换，并且即使对于较大数量的位也能够有效地补救存储单元。

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